Mesa (master): radv: refactor descriptor set userdata emission out.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: a5d10844eef71095cea3c1a921108c3bccc8ba01
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5d10844eef71095cea3c1a921108c3bccc8ba01

Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Nov 28 00:37:25 2016 +0000

radv: refactor descriptor set userdata emission out.

This just moves this into a separate function.

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied at redhat.com>

---

 src/amd/vulkan/radv_cmd_buffer.c | 37 ++++++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 89eef57..4ac5ad7 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -895,6 +895,27 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
 }
 
 static void
+radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
+				  struct radv_descriptor_set *set,
+				  unsigned idx)
+{
+	radeon_set_sh_reg_seq(cmd_buffer->cs,
+				R_00B030_SPI_SHADER_USER_DATA_PS_0 + 8 * idx, 2);
+	radeon_emit(cmd_buffer->cs, set->va);
+	radeon_emit(cmd_buffer->cs, set->va >> 32);
+
+	radeon_set_sh_reg_seq(cmd_buffer->cs,
+				R_00B130_SPI_SHADER_USER_DATA_VS_0 + 8 * idx, 2);
+	radeon_emit(cmd_buffer->cs, set->va);
+	radeon_emit(cmd_buffer->cs, set->va >> 32);
+
+	radeon_set_sh_reg_seq(cmd_buffer->cs,
+				R_00B900_COMPUTE_USER_DATA_0 + 8 * idx, 2);
+	radeon_emit(cmd_buffer->cs, set->va);
+	radeon_emit(cmd_buffer->cs, set->va >> 32);
+}
+
+static void
 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
 		     struct radv_pipeline *pipeline,
 		     VkShaderStageFlags stages)
@@ -1353,21 +1374,7 @@ void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 		if (set->descriptors[j])
 			ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
 
-	radeon_set_sh_reg_seq(cmd_buffer->cs,
-				R_00B030_SPI_SHADER_USER_DATA_PS_0 + 8 * idx, 2);
-	radeon_emit(cmd_buffer->cs, set->va);
-	radeon_emit(cmd_buffer->cs, set->va >> 32);
-
-	radeon_set_sh_reg_seq(cmd_buffer->cs,
-				R_00B130_SPI_SHADER_USER_DATA_VS_0 + 8 * idx, 2);
-	radeon_emit(cmd_buffer->cs, set->va);
-	radeon_emit(cmd_buffer->cs, set->va >> 32);
-
-	radeon_set_sh_reg_seq(cmd_buffer->cs,
-				R_00B900_COMPUTE_USER_DATA_0 + 8 * idx, 2);
-	radeon_emit(cmd_buffer->cs, set->va);
-	radeon_emit(cmd_buffer->cs, set->va >> 32);
-
+	radv_emit_descriptor_set_userdata(cmd_buffer, set, idx);
 	if(set->bo)
 		ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
 }