Mesa (master): genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: e0c1ec3b0965d573408536e6e17d41cd39f26616
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0c1ec3b0965d573408536e6e17d41cd39f26616

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Nov 21 00:11:57 2016 -0800

genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+.

This will let us avoid ifdefs.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

---

 src/intel/genxml/gen8.xml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index ebaf73a..08ee7be 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -1286,7 +1286,10 @@
     <field name="Patch URB Entry Read Offset" start="196" end="201" type="uint"/>
     <field name="Maximum Number of Threads" start="245" end="253" type="uint"/>
     <field name="Statistics Enable" start="234" end="234" type="bool"/>
-    <field name="SIMD8 Dispatch Enable" start="227" end="227" type="bool"/>
+    <field name="Dispatch Mode" start="227" end="227" type="uint" prefix="DISPATCH_MODE">
+      <value name="SIMD4X2" value="0"/>
+      <value name="SIMD8_SINGLE_PATCH" value="1"/>
+    </field>
     <field name="Compute W Coordinate Enable" start="226" end="226" type="bool"/>
     <field name="Cache Disable" start="225" end="225" type="bool"/>
     <field name="Function Enable" start="224" end="224" type="bool"/>