Mesa (master): freedreno/a5xx: fix emit for bo addresses

[Rob Clark]

Module: Mesa
Branch: master
Commit: 09202cde7e6a11b689676cafd25cc965014415f3
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=09202cde7e6a11b689676cafd25cc965014415f3

Author: Rob Clark <robdclark at gmail.com>
Date:   Wed Dec 21 22:47:42 2016 -0500

freedreno/a5xx: fix emit for bo addresses

Reloc for the buffer address is two dwords on 64b devices (a5xx+)

Signed-off-by: Rob Clark <robdclark at gmail.com>

---

 src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 1b93361..90d8168 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -95,16 +95,16 @@ static void
 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
 		uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 {
+	uint32_t anum = align(num, 2);
 	uint32_t i;
 
 	debug_assert((regid % 4) == 0);
-	debug_assert((num % 4) == 0);
 
-	OUT_PKT7(ring, CP_LOAD_STATE, 3 + num);
+	OUT_PKT7(ring, CP_LOAD_STATE, 3 + (2 * anum));
 	OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
 			CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
 			CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
-			CP_LOAD_STATE_0_NUM_UNIT(num/4));
+			CP_LOAD_STATE_0_NUM_UNIT(anum/2));
 	OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 			CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
 	OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
@@ -118,8 +118,14 @@ fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
 			}
 		} else {
 			OUT_RING(ring, 0xbad00000 | (i << 16));
+			OUT_RING(ring, 0xbad00000 | (i << 16));
 		}
 	}
+
+	for (; i < anum; i++) {
+		OUT_RING(ring, 0xffffffff);
+		OUT_RING(ring, 0xffffffff);
+	}
 }
 
 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be