Mesa (master): i965: add component packing support for load_output intrinsics
Timothy Arceri
tarceri at kemper.freedesktop.org
Wed Jul 20 23:11:09 UTC 2016
Module: Mesa
Branch: master
Commit: ad5dd39984467b29d20e03ec8bd26f6f1d2e97ad
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad5dd39984467b29d20e03ec8bd26f6f1d2e97ad
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Wed Jun 15 12:35:49 2016 +1000
i965: add component packing support for load_output intrinsics
Here we use the component qualifier (which is the first component)
as an offset when loading output varyings.
Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 38 +++++++++++++++++++++++++++-----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 65bca6d..50d73eb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2590,6 +2590,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
case nir_intrinsic_load_per_vertex_output: {
fs_reg indirect_offset = get_indirect_offset(instr);
unsigned imm_offset = instr->const_index[0];
+ unsigned first_component = nir_intrinsic_component(instr);
fs_inst *inst;
if (indirect_offset.file == BAD_FILE) {
@@ -2670,10 +2671,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
}
bld.LOAD_PAYLOAD(dst, srcs, num_components, 0);
} else {
- inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, patch_handle);
+ if (first_component != 0) {
+ unsigned read_components =
+ instr->num_components + first_component;
+ fs_reg tmp = bld.vgrf(dst.type, read_components);
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
+ patch_handle);
+ inst->regs_written = read_components;
+ for (unsigned i = 0; i < instr->num_components; i++) {
+ bld.MOV(offset(dst, bld, i),
+ offset(tmp, bld, i + first_component));
+ }
+ } else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst,
+ patch_handle);
+ inst->regs_written = instr->num_components;
+ }
inst->offset = imm_offset;
inst->mlen = 1;
- inst->regs_written = instr->num_components;
}
} else {
/* Indirect indexing - use per-slot offsets as well. */
@@ -2683,11 +2698,24 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
};
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
-
- inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst, payload);
+ if (first_component != 0) {
+ unsigned read_components =
+ instr->num_components + first_component;
+ fs_reg tmp = bld.vgrf(dst.type, read_components);
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
+ payload);
+ inst->regs_written = read_components;
+ for (unsigned i = 0; i < instr->num_components; i++) {
+ bld.MOV(offset(dst, bld, i),
+ offset(tmp, bld, i + first_component));
+ }
+ } else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
+ payload);
+ inst->regs_written = instr->num_components;
+ }
inst->offset = imm_offset;
inst->mlen = 2;
- inst->regs_written = instr->num_components;
}
break;
}
More information about the mesa-commit
mailing list