Mesa (master): anv/pipeline: Store the (set, binding, index) tripple in the bind map
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Fri Jun 10 17:03:40 UTC 2016
Module: Mesa
Branch: master
Commit: a1a25db69926604d579139d1d497f1566ec16ac7
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1a25db69926604d579139d1d497f1566ec16ac7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 6 11:12:27 2016 -0700
anv/pipeline: Store the (set, binding, index) tripple in the bind map
This way the the bind map (which we're caching) is mostly independent of
the pipeline layout. The only coupling remaining is that we pull the array
size of a binding out of the layout. However, that size is also specified
in the shader and should always match so it's not really coupled. This
rendering issues in Dota 2.
Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
Cc: "12.0" <mesa-stable at lists.freedesktop.org>
---
src/intel/vulkan/anv_cmd_buffer.c | 11 +++++++----
src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 7 ++++---
src/intel/vulkan/anv_pipeline.c | 6 ++++--
src/intel/vulkan/anv_private.h | 11 +++++++----
src/intel/vulkan/gen8_pipeline.c | 5 +++--
5 files changed, 25 insertions(+), 15 deletions(-)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c
index 3d37de2..5be5f3e 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -809,9 +809,10 @@ anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
if (binding->set == ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS) {
/* Color attachment binding */
assert(stage == MESA_SHADER_FRAGMENT);
- if (binding->offset < subpass->color_count) {
+ assert(binding->binding == 0);
+ if (binding->index < subpass->color_count) {
const struct anv_image_view *iview =
- fb->attachments[subpass->color_attachments[binding->offset]];
+ fb->attachments[subpass->color_attachments[binding->index]];
assert(iview->color_rt_surface_state.alloc_size);
surface_state = iview->color_rt_surface_state;
@@ -830,7 +831,8 @@ anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
struct anv_descriptor_set *set =
cmd_buffer->state.descriptors[binding->set];
- struct anv_descriptor *desc = &set->descriptors[binding->offset];
+ uint32_t offset = set->layout->binding[binding->binding].descriptor_index;
+ struct anv_descriptor *desc = &set->descriptors[offset + binding->index];
switch (desc->type) {
case VK_DESCRIPTOR_TYPE_SAMPLER:
@@ -927,7 +929,8 @@ anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer *cmd_buffer,
struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s];
struct anv_descriptor_set *set =
cmd_buffer->state.descriptors[binding->set];
- struct anv_descriptor *desc = &set->descriptors[binding->offset];
+ uint32_t offset = set->layout->binding[binding->binding].descriptor_index;
+ struct anv_descriptor *desc = &set->descriptors[offset + binding->index];
if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 6481269..02991be 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -318,13 +318,13 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
set_layout->binding_count) {
unsigned array_size = set_layout->binding[b].array_size;
- unsigned set_offset = set_layout->binding[b].descriptor_index;
if (set_layout->binding[b].stage[shader->stage].surface_index >= 0) {
state.set[set].surface_offsets[b] = surface;
for (unsigned i = 0; i < array_size; i++) {
map->surface_to_descriptor[surface + i].set = set;
- map->surface_to_descriptor[surface + i].offset = set_offset + i;
+ map->surface_to_descriptor[surface + i].binding = b;
+ map->surface_to_descriptor[surface + i].index = i;
}
surface += array_size;
}
@@ -333,7 +333,8 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
state.set[set].sampler_offsets[b] = sampler;
for (unsigned i = 0; i < array_size; i++) {
map->sampler_to_descriptor[sampler + i].set = set;
- map->sampler_to_descriptor[sampler + i].offset = set_offset + i;
+ map->sampler_to_descriptor[sampler + i].binding = b;
+ map->sampler_to_descriptor[sampler + i].index = i;
}
sampler += array_size;
}
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index cdbf60b..959fbbd 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -646,7 +646,8 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
for (unsigned i = 0; i < array_len; i++) {
rt_bindings[num_rts] = (struct anv_pipeline_binding) {
.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
- .offset = rt + i,
+ .binding = 0,
+ .index = rt + i,
};
}
@@ -662,7 +663,8 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
/* If we have no render targets, we need a null render target */
rt_bindings[0] = (struct anv_pipeline_binding) {
.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
- .offset = UINT16_MAX,
+ .binding = 0,
+ .index = UINT16_MAX,
};
num_rts = 1;
}
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 975cdfc..cd3588a 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1017,17 +1017,20 @@ anv_descriptor_set_destroy(struct anv_device *device,
struct anv_descriptor_pool *pool,
struct anv_descriptor_set *set);
-#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT16_MAX
+#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT8_MAX
struct anv_pipeline_binding {
/* The descriptor set this surface corresponds to. The special value of
* ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
* to a color attachment and not a regular descriptor.
*/
- uint16_t set;
+ uint8_t set;
- /* Offset into the descriptor set or attachment list. */
- uint16_t offset;
+ /* Binding in the descriptor set */
+ uint8_t binding;
+
+ /* Index in the binding */
+ uint8_t index;
};
struct anv_pipeline_layout {
diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index 1300c0d..54585c3 100644
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -137,11 +137,12 @@ emit_cb_state(struct anv_pipeline *pipeline,
/* We can have at most 8 attachments */
assert(i < 8);
- if (binding->offset >= info->attachmentCount)
+ if (binding->index >= info->attachmentCount)
continue;
+ assert(binding->binding == 0);
const VkPipelineColorBlendAttachmentState *a =
- &info->pAttachments[binding->offset];
+ &info->pAttachments[binding->index];
if (a->srcColorBlendFactor != a->srcAlphaBlendFactor ||
a->dstColorBlendFactor != a->dstAlphaBlendFactor ||
More information about the mesa-commit
mailing list