Mesa (master): 34 new commits

Wed Jun 22 19:28:48 UTC 2016

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=89ded099f840275d278c408e132ad5db39fdf5af
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 11:37:46 2016 -0700

    genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7
    
    The pack header generation scripts can't handle the case where you have
    two addresses in the same dword; they just take whatever is the last one.
    This meant that the MCS address wasn't properly getting handled.  Since we
    don't care about append counters, we can just re-arrange the XML for now.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d82322eb188f258a7dca9ea2b59cc0332dbc4d61
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 9 13:56:16 2016 -0700

    anv,isl: Lower storage image formats in anv
    
    ISL was being a bit too clever for its own good and lowering the format for
    us.  This is all well and good *if* we always want to lower it.  However,
    the GL driver selectively lowers the format depending on whether the
    surface is write-only or not.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f12773b89a409d1368ce6b3b5badb9e75bbf53
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jun 10 10:45:43 2016 -0700

    isl/state: Allow for full 31-bit buffer texture sizes
    
    Ivy Bridge and above can handle up to 2^31 elements for RAW buffer
    surfaces.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb64e666ba91ce9b1a7405a1c14d41d294062b9a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jun 10 18:28:49 2016 -0700

    isl/state: Don't use designated initializers for buffer surface state
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4061fde66e9feefa051a02fe258d69fe817e6a8c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 9 18:48:07 2016 -0700

    isl/state: Add assertions for buffer surface restrictions
    
    Acked-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce24097abe1427463ac300a686e4c36ea07464fc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 9 15:08:13 2016 -0700

    isl/state: Don't set SurfacePitch for gen9 1-D textures
    
    This field is ignored by the hardware in this case and, on very large 1-D
    textures, it can end up being larger than the maximum allowed value.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f47e23a8b6abd3bbc1d2d60c023c5a7ffaf70d72
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 14:33:40 2016 -0700

    isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7
    
    This matches better what happens on gen8 where the "Tiled Surface" and
    "Tile Walke" bits are combined into a single two-bit value.  This is also
    more consistent with what the GL driver does.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96706bad5ff37e56ee48f9bbb143d39a6e113a62
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Jun 6 18:22:21 2016 -0700

    isl/state: Emit no-op mip tail setup on SKL
    
    This hasn't ever been a problem in the past but it is recommended by the
    hardware docs.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=14d7c16e50f88720fa27722522d4ff89972a4f9d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Jun 6 18:21:17 2016 -0700

    isl/state: Only set cube face enables if usage includes CUBE_BIT
    
    It seems safe to set it all the time, but this reduces the diff between
    the way i965 does it and what ISL does.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d24e9cfa126971518be662e57021322ebf67a9a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Sat Jun 4 21:22:21 2016 -0700

    isl/state: Use the layout for computing qpitch rather than dimensions
    
    For depth/stencil 1-D textures on SKL, we want them layed out in the old
    format that has been used since gen4.  In order for the surface state
    fill-out code to handle, this it needs to distinguish based on layout
    rather than just dimensionality.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a43204afa40359f73684d3ccc7db8c4dad6288b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 08:05:45 2016 -0700

    isl/state: Set the IntegerSurfaceFormat bit on Haswell
    
    This fixes 688 Vulkan CTS tests on Haswell.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=324103da75abab5003b63ec996a2e8eb8de67049
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 14:40:47 2016 -0700

    isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=215282c9f41432a245e79cdf5f8328c6785e924a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jun 17 16:40:24 2016 -0700

    isl/state: Don't set RenderTargetViewExtent for texture surfaces
    
    The docs specify that this only matters for render targets and surfaces
    used with typed dataport messages.  On some platforms (gen4-6) the Depth
    field has more bits than RenderTargetViewExtent so we can have textures
    with more levels than we can render to.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb326f7b01daeb97e544873f20a23614ed54c548
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 15:30:00 2016 -0700

    isl/state: Set SurfaceArray based on the surface dimension
    
    According to the PRM, you can't set SurfaceArray for 3D or buffer textures.
    There doesn't seem to be a good reason not to set it when we can.  On the
    other hand, if we don't set it we can end up getting strange results for
    1-layer array textures such as textureSize() returning the wrong results.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d050ffbce950f8ececd12200145eb209819a421e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Sat Jun 4 20:48:55 2016 -0700

    isl/state: Don't force-disable L2 bypass for everything
    
    We already set the bit in the few cases where it's required by the docs so
    there's no need to set it all the time.  This has no noticable perf impact
    for Dota 2 on Vulkan with the time demo I have.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87f0ffa646e97def0f81ba2ad12eab2702dfd7b1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 2 19:02:23 2016 -0700

    isl/state: Refactor the setup of clear colors
    
    This commit switches clear colors to use #if's instead of a C if.  This
    lets us properly handle SNB where the clear color field doesn't exist.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=62a5e6e03117e5eb3f777633409cb8036be6877d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 2 19:00:10 2016 -0700

    isl/state: Refactor the per-gen isl_to_gen_h/valign tables
    
    This moves the #if's around so that halign and valign have different sets
    of #if conditions.  This also prepares us for SNB because isl_to_gen_halign
    is not defined at all on gen6.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1b0d6fb5415c874cbbd1346e50d04e33b0e9c21
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 2 18:40:07 2016 -0700

    isl/state: Return an extent3d from the halign/valign helper
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a60ae9e10ab8cd22f80dc91ba29e27db17ab3372
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 17:01:56 2016 -0700

    isl/state: Put pitch calculations together
    
    This is purely cosmetic, but it makes things look a bit more readable.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=70c8afc0c892c2a3819ea01cf5b9467d80b4d7b5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 16:58:54 2016 -0700

    isl/state: Put all dimension setup together and towards the top
    
    This is purely cosmetic, but it makes things look a bit more readable.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e66e70ef47907264757751206878b703bd95390b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 17:14:39 2016 -0700

    isl/state: Put surface format setup at the top
    
    This is purely cosmetic, but it makes things look a bit more readable.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=39baea551fe228cfc4647d6a56e80639b7129b6a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 16:55:21 2016 -0700

    isl/state: Remove some unused fields
    
    They're already zero-initialized and we have no plans of doing anything
    more interesting with them.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=caf2af4181c66df8af31662de22120dcf1d16c7c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 7 16:53:19 2016 -0700

    isl/state: Don't use designated initializers for the surface state
    
    While designated initializers are nice, they also force us to put some
    things in the initializer and some things later.  Surface state setup is
    complicated enough that this really hurts readability in the long run.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=de1d194856ddcfc946df2df0f076cb42ff1c165d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 2 18:43:59 2016 -0700

    genxml/gen8,9: Prefix the multisample format enum with MSFMT
    
    This is what gen7 does and it's nice to have a prefix
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=320de71858cc1ec73e2735923ac30ef45cbc1957
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jun 10 14:44:32 2016 -0700

    i965/blorp: Only set src_z for gen8+ 3D textures
    
    Otherwise, we end up with a bogus value in the third component.  On gen6-7
    where we always use 2D textures, this can cause problems if the
    SurfaceArray bit is set in the SURFACE_STATE.
    
    Acked-by: Chad Versace <chad.versace at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=664dc89a1baede86da193a24d27d6314fa0f662e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Sat Jun 11 07:51:30 2016 -0700

    i965/gen7,8: Set SURFACE_IS_ARRAY for all non-3D texture types
    
    There's no real reason why we shouldn't set this bit.  It does affect how
    the sampler operates a bit but since you can have a 2D non-array view of a
    2D_ARRAY texture that distinction is very weak.  Also, this is what ISL
    will do and we would like this change to be isolated from using ISL.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a1cc94d27c80929d91e38b4843333a5408d563e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jun 10 21:11:02 2016 -0700

    i965/gen4: Subtract 1 from buffer sizes
    
    The PRM states that the values put in Width, Height, and Depth should be
    various bits from the value size - 1.  We seem to have done this wrong
    more-or-less from the start.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8580b8f981a48dd481c62292c7d618a4860dfad
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 9 15:52:52 2016 -0700

    i965: Remove fake W-tiled render target support
    
    This hasn't been used since 1cfb4bc890b8 where we deleted the meta stencil
    blit path.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0195299c868ec99bc6c595c641da81bb2632252e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Jun 6 19:15:39 2016 -0700

    i965/fs: Use a default Y coordinate of 0 for TXF on gen9+
    
    Previously, we were incrementing length but not actually putting anything
    in the Y coordinate.  This meant that 1-D TXF operations had a garbage
    array index.  If the surface is emitted as 1-D non-array, the coordinate
    gets discarded and it works fine.  If it happens to be bound as an array
    surface, it may count as an out-of-bounds array access and you get zero.
    
    Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1436238b75e0352439306f120ac1ca03c9fc7df3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Sat Jun 4 14:32:37 2016 -0700

    i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=620f81d2edb20ffd9803ee318f60845441459fac
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Jun 3 23:25:19 2016 -0700

    i965/blorp/gen8: Use the correct max level and layer in emit_surface_states
    
    We were adding in the base which is wrong because the values given in the
    miptree are relative to zero and not the base layer/level.
    
    Reviewed-by: Chad Versace <chad.versace at intel.com>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ba88bce64b343761aabe3a6c7ee285c6020a959
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Jun 9 14:57:33 2016 -0700

    i965: Drop the maximum 3D texture size to 512 on Sandy Bridge
    
    The RenderTargetViewExtent field of RENDER_SURFACE_STATE is supposed to be
    set to the depth of a 3-D texture when rendering.  Unfortunatley, that
    field is only 9 bits on Sandy Bridge and prior so we can't actually bind
    a 3-D texturing for rendering if it has depth > 512.  On Ivy Bridge, this
    field was bumpped to 11 bits so we can go all the way up to 2048.  On Iron
    Lake and prior, we don't support layered rendering and we use OffsetX/Y
    hacks to render to particular layers so 2048 is ok there too.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f9cd74aab021da81a7e5a2f0fbf66213471628f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Jun 22 11:11:29 2016 -0700

    i965/gen4-6: Handle gl_texture_object::BaseLevel and MinLayer correctly
    
    This is basically a direct translation of what we do for gen7.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee39d3ba918de9d52d79bdee6db2c120bcf0f28e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 21 21:58:23 2016 -0700

    i965/gen4: Pull texture formats from the texture object not the miptree
    
    This makes texture views sort-of work.  It doesn't add full texture view
    support for gen4-5 but it is enough to fix the GL_ARB_copy_image formats
    piglit test on Iron Lake.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83036
    Cc: "11.1 11.2 12.0" <mesa-stable at lists.freedesktop.org>