Mesa (master): radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 2aa0485902cdb4cd02b72627a760b00e71bffecf
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2aa0485902cdb4cd02b72627a760b00e71bffecf

Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date:   Thu Jun 23 15:00:53 2016 +0200

radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris

The non-MULTI variants will be removed in Polaris firmware.

Cc: 12.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>

---

 src/gallium/drivers/radeonsi/si_state_draw.c | 46 ++++++++++++++++++++++------
 1 file changed, 36 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 641becf..5273718 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -596,11 +596,24 @@ static void si_emit_draw_packets(struct si_context *sctx,
 			radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
 			radeon_emit(cs, index_max_size);
 
-			radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
-			radeon_emit(cs, info->indirect_offset);
-			radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
-			radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
-			radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+			if (sctx->b.family < CHIP_POLARIS10) {
+				radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
+				radeon_emit(cs, info->indirect_offset);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+			} else {
+				radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI, 8, render_cond_bit));
+				radeon_emit(cs, info->indirect_offset);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, 0); /* draw_index */
+				radeon_emit(cs, 1); /* count */
+				radeon_emit(cs, 0); /* count_addr -- disabled */
+				radeon_emit(cs, 0);
+				radeon_emit(cs, 16); /* stride */
+				radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+			}
 		} else {
 			index_va += info->start * ib->index_size;
 
@@ -623,11 +636,24 @@ static void si_emit_draw_packets(struct si_context *sctx,
 			radeon_emit(cs, indirect_va);
 			radeon_emit(cs, indirect_va >> 32);
 
-			radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
-			radeon_emit(cs, info->indirect_offset);
-			radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
-			radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
-			radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+			if (sctx->b.family < CHIP_POLARIS10) {
+				radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
+				radeon_emit(cs, info->indirect_offset);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+			} else {
+				radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT_MULTI, 8, render_cond_bit));
+				radeon_emit(cs, info->indirect_offset);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
+				radeon_emit(cs, 0); /* draw_index */
+				radeon_emit(cs, 1); /* count */
+				radeon_emit(cs, 0); /* count_addr -- disabled */
+				radeon_emit(cs, 0);
+				radeon_emit(cs, 16); /* stride */
+				radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
+			}
 		} else {
 			radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
 			radeon_emit(cs, info->count);