Mesa (master): i965: Move inst_info from brw_eu_validate.c to brw_eu.c.
Matt Turner
mattst88 at kemper.freedesktop.org
Wed May 4 05:59:50 UTC 2016
Module: Mesa
Branch: master
Commit: d01596613b6b7831a3c6a596108a83340f8bf657
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d01596613b6b7831a3c6a596108a83340f8bf657
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 29 16:07:44 2016 -0700
i965: Move inst_info from brw_eu_validate.c to brw_eu.c.
Drop the uses of 'enum gen' to a plain int, so that we don't have to
expose the bitfield definitions and GEN_GE/GEN_LE macros to other users
of brw_eu.h. As a result, s/.gen/.gens/ to avoid confusion with
devinfo->gen.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_eu.c | 239 +++++++++++++++++++++++++++
src/mesa/drivers/dri/i965/brw_eu.h | 8 +
src/mesa/drivers/dri/i965/brw_eu_validate.c | 247 +---------------------------
3 files changed, 249 insertions(+), 245 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 279e957..80ce98e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -340,6 +340,245 @@ brw_disassemble(const struct brw_device_info *devinfo,
}
}
+enum gen {
+ GEN4 = (1 << 0),
+ GEN45 = (1 << 1),
+ GEN5 = (1 << 2),
+ GEN6 = (1 << 3),
+ GEN7 = (1 << 4),
+ GEN75 = (1 << 5),
+ GEN8 = (1 << 6),
+ GEN9 = (1 << 7),
+ GEN_ALL = ~0
+};
+
+#define GEN_GE(gen) (~((gen) - 1) | gen)
+#define GEN_LE(gen) (((gen) - 1) | gen)
+
+const struct inst_info inst_info[128] = {
+ [BRW_OPCODE_ILLEGAL] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_MOV] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SEL] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_MOVI] = {
+ .gens = GEN_GE(GEN45),
+ },
+ [BRW_OPCODE_NOT] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_AND] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_OR] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_XOR] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SHR] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SHL] = {
+ .gens = GEN_ALL,
+ },
+ /* BRW_OPCODE_DIM / BRW_OPCODE_SMOV */
+ /* Reserved - 11 */
+ [BRW_OPCODE_ASR] = {
+ .gens = GEN_ALL,
+ },
+ /* Reserved - 13-15 */
+ [BRW_OPCODE_CMP] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_CMPN] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_CSEL] = {
+ .gens = GEN_GE(GEN8),
+ },
+ [BRW_OPCODE_F32TO16] = {
+ .gens = GEN7 | GEN75,
+ },
+ [BRW_OPCODE_F16TO32] = {
+ .gens = GEN7 | GEN75,
+ },
+ /* Reserved - 21-22 */
+ [BRW_OPCODE_BFREV] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_BFE] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_BFI1] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_BFI2] = {
+ .gens = GEN_GE(GEN7),
+ },
+ /* Reserved - 27-31 */
+ [BRW_OPCODE_JMPI] = {
+ .gens = GEN_ALL,
+ },
+ /* BRW_OPCODE_BRD */
+ [BRW_OPCODE_IF] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_IFF] = { /* also BRW_OPCODE_BRC */
+ .gens = GEN_LE(GEN5),
+ },
+ [BRW_OPCODE_ELSE] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_ENDIF] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_DO] = { /* also BRW_OPCODE_CASE */
+ .gens = GEN_LE(GEN5),
+ },
+ [BRW_OPCODE_WHILE] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_BREAK] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_CONTINUE] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_HALT] = {
+ .gens = GEN_ALL,
+ },
+ /* BRW_OPCODE_CALLA */
+ /* BRW_OPCODE_MSAVE / BRW_OPCODE_CALL */
+ /* BRW_OPCODE_MREST / BRW_OPCODE_RET */
+ /* BRW_OPCODE_PUSH / BRW_OPCODE_FORK / BRW_OPCODE_GOTO */
+ /* BRW_OPCODE_POP */
+ [BRW_OPCODE_WAIT] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SEND] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SENDC] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SENDS] = {
+ .gens = GEN_GE(GEN9),
+ },
+ [BRW_OPCODE_SENDSC] = {
+ .gens = GEN_GE(GEN9),
+ },
+ /* Reserved 53-55 */
+ [BRW_OPCODE_MATH] = {
+ .gens = GEN_GE(GEN6),
+ },
+ /* Reserved 57-63 */
+ [BRW_OPCODE_ADD] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_MUL] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_AVG] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_FRC] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_RNDU] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_RNDD] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_RNDE] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_RNDZ] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_MAC] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_MACH] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_LZD] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_FBH] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_FBL] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_CBIT] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_ADDC] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_SUBB] = {
+ .gens = GEN_GE(GEN7),
+ },
+ [BRW_OPCODE_SAD2] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_SADA2] = {
+ .gens = GEN_ALL,
+ },
+ /* Reserved 82-83 */
+ [BRW_OPCODE_DP4] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_DPH] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_DP3] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_DP2] = {
+ .gens = GEN_ALL,
+ },
+ /* Reserved 88 */
+ [BRW_OPCODE_LINE] = {
+ .gens = GEN_ALL,
+ },
+ [BRW_OPCODE_PLN] = {
+ .gens = GEN_GE(GEN45),
+ },
+ [BRW_OPCODE_MAD] = {
+ .gens = GEN_GE(GEN6),
+ },
+ [BRW_OPCODE_LRP] = {
+ .gens = GEN_GE(GEN6),
+ },
+ /* Reserved 93-124 */
+ /* BRW_OPCODE_NENOP */
+ [BRW_OPCODE_NOP] = {
+ .gens = GEN_ALL,
+ },
+};
+
+int
+gen_from_devinfo(const struct brw_device_info *devinfo)
+{
+ switch (devinfo->gen) {
+ case 4: return devinfo->is_g4x ? GEN45 : GEN4;
+ case 5: return GEN5;
+ case 6: return GEN6;
+ case 7: return devinfo->is_haswell ? GEN75 : GEN7;
+ case 8: return GEN8;
+ case 9: return GEN9;
+ default:
+ unreachable("not reached");
+ }
+}
+
/* Return the matching opcode_desc for the specified opcode number and
* hardware generation, or NULL if the opcode is not supported by the device.
* XXX -- Actually check whether the opcode is supported.
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 563a105..a1434e4 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -545,6 +545,14 @@ next_offset(const struct brw_device_info *devinfo, void *store, int offset)
return offset + 16;
}
+struct inst_info {
+ int gens;
+};
+
+extern const struct inst_info inst_info[128];
+
+int gen_from_devinfo(const struct brw_device_info *devinfo);
+
const struct opcode_desc *
brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c b/src/mesa/drivers/dri/i965/brw_eu_validate.c
index 75e161b..b87b32e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_validate.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_validate.c
@@ -68,234 +68,6 @@ src1_is_null(const struct brw_device_info *devinfo, const brw_inst *inst)
brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
}
-enum gen {
- GEN4 = (1 << 0),
- GEN45 = (1 << 1),
- GEN5 = (1 << 2),
- GEN6 = (1 << 3),
- GEN7 = (1 << 4),
- GEN75 = (1 << 5),
- GEN8 = (1 << 6),
- GEN9 = (1 << 7),
- GEN_ALL = ~0
-};
-
-#define GEN_GE(gen) (~((gen) - 1) | gen)
-#define GEN_LE(gen) (((gen) - 1) | gen)
-
-struct inst_info {
- enum gen gen;
-};
-
-static const struct inst_info inst_info[128] = {
- [BRW_OPCODE_ILLEGAL] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_MOV] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SEL] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_MOVI] = {
- .gen = GEN_GE(GEN45),
- },
- [BRW_OPCODE_NOT] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_AND] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_OR] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_XOR] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SHR] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SHL] = {
- .gen = GEN_ALL,
- },
- /* BRW_OPCODE_DIM / BRW_OPCODE_SMOV */
- /* Reserved - 11 */
- [BRW_OPCODE_ASR] = {
- .gen = GEN_ALL,
- },
- /* Reserved - 13-15 */
- [BRW_OPCODE_CMP] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_CMPN] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_CSEL] = {
- .gen = GEN_GE(GEN8),
- },
- [BRW_OPCODE_F32TO16] = {
- .gen = GEN7 | GEN75,
- },
- [BRW_OPCODE_F16TO32] = {
- .gen = GEN7 | GEN75,
- },
- /* Reserved - 21-22 */
- [BRW_OPCODE_BFREV] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_BFE] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_BFI1] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_BFI2] = {
- .gen = GEN_GE(GEN7),
- },
- /* Reserved - 27-31 */
- [BRW_OPCODE_JMPI] = {
- .gen = GEN_ALL,
- },
- /* BRW_OPCODE_BRD */
- [BRW_OPCODE_IF] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_IFF] = { /* also BRW_OPCODE_BRC */
- .gen = GEN_LE(GEN5),
- },
- [BRW_OPCODE_ELSE] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_ENDIF] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_DO] = { /* also BRW_OPCODE_CASE */
- .gen = GEN_LE(GEN5),
- },
- [BRW_OPCODE_WHILE] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_BREAK] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_CONTINUE] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_HALT] = {
- .gen = GEN_ALL,
- },
- /* BRW_OPCODE_CALLA */
- /* BRW_OPCODE_MSAVE / BRW_OPCODE_CALL */
- /* BRW_OPCODE_MREST / BRW_OPCODE_RET */
- /* BRW_OPCODE_PUSH / BRW_OPCODE_FORK / BRW_OPCODE_GOTO */
- /* BRW_OPCODE_POP */
- [BRW_OPCODE_WAIT] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SEND] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SENDC] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SENDS] = {
- .gen = GEN_GE(GEN9),
- },
- [BRW_OPCODE_SENDSC] = {
- .gen = GEN_GE(GEN9),
- },
- /* Reserved 53-55 */
- [BRW_OPCODE_MATH] = {
- .gen = GEN_GE(GEN6),
- },
- /* Reserved 57-63 */
- [BRW_OPCODE_ADD] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_MUL] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_AVG] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_FRC] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_RNDU] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_RNDD] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_RNDE] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_RNDZ] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_MAC] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_MACH] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_LZD] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_FBH] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_FBL] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_CBIT] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_ADDC] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_SUBB] = {
- .gen = GEN_GE(GEN7),
- },
- [BRW_OPCODE_SAD2] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_SADA2] = {
- .gen = GEN_ALL,
- },
- /* Reserved 82-83 */
- [BRW_OPCODE_DP4] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_DPH] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_DP3] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_DP2] = {
- .gen = GEN_ALL,
- },
- /* Reserved 88 */
- [BRW_OPCODE_LINE] = {
- .gen = GEN_ALL,
- },
- [BRW_OPCODE_PLN] = {
- .gen = GEN_GE(GEN45),
- },
- [BRW_OPCODE_MAD] = {
- .gen = GEN_GE(GEN6),
- },
- [BRW_OPCODE_LRP] = {
- .gen = GEN_GE(GEN6),
- },
- /* Reserved 93-124 */
- /* BRW_OPCODE_NENOP */
- [BRW_OPCODE_NOP] = {
- .gen = GEN_ALL,
- },
-};
-
static unsigned
num_sources_from_inst(const struct brw_device_info *devinfo,
const brw_inst *inst)
@@ -345,27 +117,12 @@ num_sources_from_inst(const struct brw_device_info *devinfo,
}
}
-static enum gen
-gen_from_devinfo(const struct brw_device_info *devinfo)
-{
- switch (devinfo->gen) {
- case 4: return devinfo->is_g4x ? GEN45 : GEN4;
- case 5: return GEN5;
- case 6: return GEN6;
- case 7: return devinfo->is_haswell ? GEN75 : GEN7;
- case 8: return GEN8;
- case 9: return GEN9;
- default:
- unreachable("not reached");
- }
-}
-
static bool
is_unsupported_inst(const struct brw_device_info *devinfo,
const brw_inst *inst)
{
- enum gen gen = gen_from_devinfo(devinfo);
- return (inst_info[brw_inst_opcode(devinfo, inst)].gen & gen) == 0;
+ int gen = gen_from_devinfo(devinfo);
+ return (inst_info[brw_inst_opcode(devinfo, inst)].gens & gen) == 0;
}
bool
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