Mesa (master): i965; Move brw_meta_get_*_rect to brw_meta_util.c
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Sat May 14 23:01:11 UTC 2016
Module: Mesa
Branch: master
Commit: 36529f670fad3872b8b54e1bf6b3113ad2a737a0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36529f670fad3872b8b54e1bf6b3113ad2a737a0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu May 12 15:15:03 2016 -0700
i965; Move brw_meta_get_*_rect to brw_meta_util.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 180 ------------------------
src/mesa/drivers/dri/i965/brw_meta_util.c | 180 ++++++++++++++++++++++++
2 files changed, 180 insertions(+), 180 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 217097e..2d42d51 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -216,149 +216,6 @@ brw_draw_rectlist(struct brw_context *brw, struct rect *rect, int num_instances)
NULL, 0, NULL);
}
-void
-brw_get_fast_clear_rect(const struct brw_context *brw,
- const struct gl_framebuffer *fb,
- const struct intel_mipmap_tree* mt,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1)
-{
- unsigned int x_align, y_align;
- unsigned int x_scaledown, y_scaledown;
-
- /* Only single sampled surfaces need to (and actually can) be resolved. */
- if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
- intel_miptree_is_lossless_compressed(brw, mt)) {
- /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
- * Target(s)", beneath the "Fast Color Clear" bullet (p327):
- *
- * Clear pass must have a clear rectangle that must follow
- * alignment rules in terms of pixels and lines as shown in the
- * table below. Further, the clear-rectangle height and width
- * must be multiple of the following dimensions. If the height
- * and width of the render target being cleared do not meet these
- * requirements, an MCS buffer can be created such that it
- * follows the requirement and covers the RT.
- *
- * The alignment size in the table that follows is related to the
- * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
- * with X alignment multiplied by 16 and Y alignment multiplied by 32.
- */
- intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
- x_align *= 16;
-
- /* SKL+ line alignment requirement for Y-tiled are half those of the prior
- * generations.
- */
- if (brw->gen >= 9)
- y_align *= 16;
- else
- y_align *= 32;
-
- /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
- * Target(s)", beneath the "Fast Color Clear" bullet (p327):
- *
- * In order to optimize the performance MCS buffer (when bound to
- * 1X RT) clear similarly to MCS buffer clear for MSRT case,
- * clear rect is required to be scaled by the following factors
- * in the horizontal and vertical directions:
- *
- * The X and Y scale down factors in the table that follows are each
- * equal to half the alignment value computed above.
- */
- x_scaledown = x_align / 2;
- y_scaledown = y_align / 2;
-
- /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
- * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
- * Clear of Non-MultiSampled Render Target Restrictions":
- *
- * Clear rectangle must be aligned to two times the number of
- * pixels in the table shown below due to 16x16 hashing across the
- * slice.
- */
- x_align *= 2;
- y_align *= 2;
- } else {
- /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
- * Target(s)", beneath the "MSAA Compression" bullet (p326):
- *
- * Clear pass for this case requires that scaled down primitive
- * is sent down with upper left co-ordinate to coincide with
- * actual rectangle being cleared. For MSAA, clear rectangle’s
- * height and width need to as show in the following table in
- * terms of (width,height) of the RT.
- *
- * MSAA Width of Clear Rect Height of Clear Rect
- * 2X Ceil(1/8*width) Ceil(1/2*height)
- * 4X Ceil(1/8*width) Ceil(1/2*height)
- * 8X Ceil(1/2*width) Ceil(1/2*height)
- * 16X width Ceil(1/2*height)
- *
- * The text "with upper left co-ordinate to coincide with actual
- * rectangle being cleared" is a little confusing--it seems to imply
- * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
- * feed the pipeline using the rectangle (x,y) to
- * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
- * the number of samples. Experiments indicate that this is not
- * quite correct; actually, what the hardware appears to do is to
- * align whatever rectangle is sent down the pipeline to the nearest
- * multiple of 2x2 blocks, and then scale it up by a factor of N
- * horizontally and 2 vertically. So the resulting alignment is 4
- * vertically and either 4 or 16 horizontally, and the scaledown
- * factor is 2 vertically and either 2 or 8 horizontally.
- */
- switch (mt->num_samples) {
- case 2:
- case 4:
- x_scaledown = 8;
- break;
- case 8:
- x_scaledown = 2;
- break;
- case 16:
- x_scaledown = 1;
- break;
- default:
- unreachable("Unexpected sample count for fast clear");
- }
- y_scaledown = 2;
- x_align = x_scaledown * 2;
- y_align = y_scaledown * 2;
- }
-
- *x0 = fb->_Xmin;
- *x1 = fb->_Xmax;
- if (fb->Name != 0) {
- *y0 = fb->_Ymin;
- *y1 = fb->_Ymax;
- } else {
- *y0 = fb->Height - fb->_Ymax;
- *y1 = fb->Height - fb->_Ymin;
- }
-
- *x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
- *y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
- *x1 = ALIGN(*x1, x_align) / x_scaledown;
- *y1 = ALIGN(*y1, y_align) / y_scaledown;
-}
-
-void
-brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1)
-{
- *x0 = fb->_Xmin;
- *x1 = fb->_Xmax;
- if (fb->Name != 0) {
- *y0 = fb->_Ymin;
- *y1 = fb->_Ymax;
- } else {
- *y0 = fb->Height - fb->_Ymax;
- *y1 = fb->Height - fb->_Ymin;
- }
-}
-
/**
* Convert the given color to a bitfield suitable for ORing into DWORD 7 of
* SURFACE_STATE (DWORD 12-15 on SKL+).
@@ -770,43 +627,6 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
}
void
-brw_get_resolve_rect(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1)
-{
- unsigned x_align, y_align;
- unsigned x_scaledown, y_scaledown;
-
- /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
- *
- * A rectangle primitive must be scaled down by the following factors
- * with respect to render target being resolved.
- *
- * The scaledown factors in the table that follows are related to the
- * alignment size returned by intel_get_non_msrt_mcs_alignment() by a
- * multiplier. For IVB and HSW, we divide by two, for BDW we multiply
- * by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical scaling
- * by a factor of 2.
- */
-
- intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
- if (brw->gen >= 9) {
- x_scaledown = x_align * 8;
- y_scaledown = y_align * 8;
- } else if (brw->gen >= 8) {
- x_scaledown = x_align * 8;
- y_scaledown = y_align * 16;
- } else {
- x_scaledown = x_align / 2;
- y_scaledown = y_align / 2;
- }
- *x0 = *y0 = 0;
- *x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
- *y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
-}
-
-void
brw_meta_resolve_color(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 432321d..a5d7b11 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -366,3 +366,183 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
}
return true;
}
+
+void
+brw_get_fast_clear_rect(const struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ const struct intel_mipmap_tree* mt,
+ unsigned *x0, unsigned *y0,
+ unsigned *x1, unsigned *y1)
+{
+ unsigned int x_align, y_align;
+ unsigned int x_scaledown, y_scaledown;
+
+ /* Only single sampled surfaces need to (and actually can) be resolved. */
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
+ intel_miptree_is_lossless_compressed(brw, mt)) {
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "Fast Color Clear" bullet (p327):
+ *
+ * Clear pass must have a clear rectangle that must follow
+ * alignment rules in terms of pixels and lines as shown in the
+ * table below. Further, the clear-rectangle height and width
+ * must be multiple of the following dimensions. If the height
+ * and width of the render target being cleared do not meet these
+ * requirements, an MCS buffer can be created such that it
+ * follows the requirement and covers the RT.
+ *
+ * The alignment size in the table that follows is related to the
+ * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
+ * with X alignment multiplied by 16 and Y alignment multiplied by 32.
+ */
+ intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
+ x_align *= 16;
+
+ /* SKL+ line alignment requirement for Y-tiled are half those of the prior
+ * generations.
+ */
+ if (brw->gen >= 9)
+ y_align *= 16;
+ else
+ y_align *= 32;
+
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "Fast Color Clear" bullet (p327):
+ *
+ * In order to optimize the performance MCS buffer (when bound to
+ * 1X RT) clear similarly to MCS buffer clear for MSRT case,
+ * clear rect is required to be scaled by the following factors
+ * in the horizontal and vertical directions:
+ *
+ * The X and Y scale down factors in the table that follows are each
+ * equal to half the alignment value computed above.
+ */
+ x_scaledown = x_align / 2;
+ y_scaledown = y_align / 2;
+
+ /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
+ * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+ * Clear of Non-MultiSampled Render Target Restrictions":
+ *
+ * Clear rectangle must be aligned to two times the number of
+ * pixels in the table shown below due to 16x16 hashing across the
+ * slice.
+ */
+ x_align *= 2;
+ y_align *= 2;
+ } else {
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
+ * Target(s)", beneath the "MSAA Compression" bullet (p326):
+ *
+ * Clear pass for this case requires that scaled down primitive
+ * is sent down with upper left co-ordinate to coincide with
+ * actual rectangle being cleared. For MSAA, clear rectangle’s
+ * height and width need to as show in the following table in
+ * terms of (width,height) of the RT.
+ *
+ * MSAA Width of Clear Rect Height of Clear Rect
+ * 2X Ceil(1/8*width) Ceil(1/2*height)
+ * 4X Ceil(1/8*width) Ceil(1/2*height)
+ * 8X Ceil(1/2*width) Ceil(1/2*height)
+ * 16X width Ceil(1/2*height)
+ *
+ * The text "with upper left co-ordinate to coincide with actual
+ * rectangle being cleared" is a little confusing--it seems to imply
+ * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
+ * feed the pipeline using the rectangle (x,y) to
+ * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
+ * the number of samples. Experiments indicate that this is not
+ * quite correct; actually, what the hardware appears to do is to
+ * align whatever rectangle is sent down the pipeline to the nearest
+ * multiple of 2x2 blocks, and then scale it up by a factor of N
+ * horizontally and 2 vertically. So the resulting alignment is 4
+ * vertically and either 4 or 16 horizontally, and the scaledown
+ * factor is 2 vertically and either 2 or 8 horizontally.
+ */
+ switch (mt->num_samples) {
+ case 2:
+ case 4:
+ x_scaledown = 8;
+ break;
+ case 8:
+ x_scaledown = 2;
+ break;
+ case 16:
+ x_scaledown = 1;
+ break;
+ default:
+ unreachable("Unexpected sample count for fast clear");
+ }
+ y_scaledown = 2;
+ x_align = x_scaledown * 2;
+ y_align = y_scaledown * 2;
+ }
+
+ *x0 = fb->_Xmin;
+ *x1 = fb->_Xmax;
+ if (fb->Name != 0) {
+ *y0 = fb->_Ymin;
+ *y1 = fb->_Ymax;
+ } else {
+ *y0 = fb->Height - fb->_Ymax;
+ *y1 = fb->Height - fb->_Ymin;
+ }
+
+ *x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
+ *y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
+ *x1 = ALIGN(*x1, x_align) / x_scaledown;
+ *y1 = ALIGN(*y1, y_align) / y_scaledown;
+}
+
+void
+brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
+ unsigned *x0, unsigned *y0,
+ unsigned *x1, unsigned *y1)
+{
+ *x0 = fb->_Xmin;
+ *x1 = fb->_Xmax;
+ if (fb->Name != 0) {
+ *y0 = fb->_Ymin;
+ *y1 = fb->_Ymax;
+ } else {
+ *y0 = fb->Height - fb->_Ymax;
+ *y1 = fb->Height - fb->_Ymin;
+ }
+}
+
+void
+brw_get_resolve_rect(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt,
+ unsigned *x0, unsigned *y0,
+ unsigned *x1, unsigned *y1)
+{
+ unsigned x_align, y_align;
+ unsigned x_scaledown, y_scaledown;
+
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
+ *
+ * A rectangle primitive must be scaled down by the following factors
+ * with respect to render target being resolved.
+ *
+ * The scaledown factors in the table that follows are related to the
+ * alignment size returned by intel_get_non_msrt_mcs_alignment() by a
+ * multiplier. For IVB and HSW, we divide by two, for BDW we multiply
+ * by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical scaling
+ * by a factor of 2.
+ */
+
+ intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
+ if (brw->gen >= 9) {
+ x_scaledown = x_align * 8;
+ y_scaledown = y_align * 8;
+ } else if (brw->gen >= 8) {
+ x_scaledown = x_align * 8;
+ y_scaledown = y_align * 16;
+ } else {
+ x_scaledown = x_align / 2;
+ y_scaledown = y_align / 2;
+ }
+ *x0 = *y0 = 0;
+ *x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
+ *y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
+}
More information about the mesa-commit
mailing list