Mesa (master): i965/fs: calculate first non-payload GRF using attrib slots
Alejandro Pinheiro
apinheiro at kemper.freedesktop.org
Tue May 17 11:01:11 UTC 2016
Module: Mesa
Branch: master
Commit: 7ea09511ca4f58640063cc1ee08386cce5300535
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ea09511ca4f58640063cc1ee08386cce5300535
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date: Mon Apr 4 12:47:57 2016 +0200
i965/fs: calculate first non-payload GRF using attrib slots
When computing where the first non-payload GRF starts, we can't rely on
the number of attributes, as each attribute can be using 1 or 2 slots
depending on whether they are a dvec3/4 or other.
Instead, we need to use the number of slots used by the attributes.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h
index a2148ae..0db1d0d 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -611,6 +611,7 @@ struct brw_vs_prog_data {
GLbitfield64 inputs_read;
unsigned nr_attributes;
+ unsigned nr_attribute_slots;
bool uses_vertexid;
bool uses_instanceid;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e8baf6c..bf3a467 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1768,7 +1768,7 @@ fs_visitor::assign_vs_urb_setup()
assert(stage == MESA_SHADER_VERTEX);
/* Each attribute is 4 regs. */
- this->first_non_payload_grf += 4 * vs_prog_data->nr_attributes;
+ this->first_non_payload_grf += 4 * vs_prog_data->nr_attribute_slots;
assert(vs_prog_data->base.urb_read_length <= 15);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index ac8dd6f..162b481 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2120,6 +2120,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
DIV_ROUND_UP(MAX2(nr_attribute_slots, 1), 2);
prog_data->nr_attributes = nr_attributes;
+ prog_data->nr_attribute_slots = nr_attribute_slots;
/* Since vertex shaders reuse the same VUE entry for inputs and outputs
* (overwriting the original contents), we need to make sure the size is
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