Mesa (master): 21 new commits

Tue May 24 02:12:48 UTC 2016

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f5ccaf4dcdb308e5ce9f680b5ae267abb9c130a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 20 16:10:41 2016 -0700

    i965: Use ISL for surface format introspection
    
    With this, we can delete the surface format table in brw_surface_formats.c
    because all of the information we need is now in ISL.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d68acde1cb4825589849f512047a8cb31b3b5a35
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 20 16:07:04 2016 -0700

    anv/formats: Use isl_format_supports* for format introspection

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7374d006b6d1f09483c986a3f1b5f55cce007b04
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 20 15:42:34 2016 -0700

    isl: Add per-gen format introspection
    
    This is just a copy-and-paste from brw_surface_formats.c.  For the
    supports_vertex_fetch function, we do a bit more work so that it properly
    handles Bay Trail.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=03a82dc5d1056e733c39326983b1b1755da10d48
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 20 15:41:57 2016 -0700

    isl: Add the ISL_FORMAT_R32G32_FLOAT_LD format

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=35a514e6ff9a33fd5a4a172c7dfa98520e465d36
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 20 15:41:20 2016 -0700

    isl: Add support for quering the string name of a format

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=75d10dff0bda6de2a31e26eb8e950adc5fd3994e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue May 17 13:46:43 2016 -0700

    i965: Enable ARB/KHR_robust_buffer_access_behavior on BYT and HSW+
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a092fcf3bd673074d5b0b6794858c3f050aa969
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 20 16:45:31 2016 -0700

    main: Add extension enable bits for KHR_robust_buffer_access_behavior
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=66e137ecf1e6a77374c0278a02246cff3cab0355
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 14:56:19 2016 -0700

    nir/lower_samplers: Protect against sampler index overflow
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=27b9481d03959a7bee6d906c62b4a519b6b1dc38
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 20:28:07 2016 -0700

    glsl: Add an option to clamp block indices when lowering UBO/SSBOs
    
    This prevents array overflow when the block is actually an array of UBOs or
    SSBOs.  On some hardware such as i965, such overflows can cause GPU hangs.
    
    Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac242aac3d2c38fd6843d85363a455271b1348c2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 20:29:59 2016 -0700

    glsl/linker: Add a helper variable for compiler options
    
    Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aec10a1d5b4a0802f6f09d1b83c79f53ecd3d29f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue May 17 15:34:40 2016 -0700

    i965/draw: Use the real size for index buffers
    
    Previously, we were using the size of the whole BO which may be
    substantially larger than the actual index buffer size.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c8dfa78b98a12c1c5f74d11433c8554d4c90657
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue May 17 15:34:07 2016 -0700

    i965/draw: Use the real size for vertex buffers
    
    Previously, we were using the size of the BO which may be substantially
    larger than the actual vertex buffer size.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a643bc62463efbd88e34a85cda50a19d8ace6292
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu May 19 14:33:50 2016 -0700

    i965/draw: Use 3-channel formats for vertex fetch when possible.
    
    For a long time, several of the 3-channel vertex formats didn't exist so we
    faked them with 4-channel versions.  Starting with Sandy Bridge, we can use
    R16G16B16_FLOAT and 8 and 16-bit integer formats become available on
    Haswell and Bay Trail.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab3d8d5ea43501d7f0716e889e0ade505aaf9463
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu May 19 15:43:43 2016 -0700

    i965/surface_formats: Update the VB column for new formats added on BYT
    
    Bay Trail and Haswell added a bunch of new vertex formats.  There was also
    the addition of 64-bit passthrough formats for BDW+.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5b4ab2c5f700087ac09238e3cf8252aa3d31d54
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 13:05:48 2016 -0700

    i965/draw: Properly handle rounding when dividing by InstanceDivisor
    
    The old code always divided rounded down and then subtracted 1.  What we
    wanted was to divide rounded up and then subtract 1 which is equivalent to
    subtracting 1 and then dividing rounded down.
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad42ab473cb327e9f0498bda9d92cccc4279a0e8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 13:05:02 2016 -0700

    i965/draw: Account for BaseInstance in VBO bounds
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad3deec8ca9813a746ac833e6a0cc2ed13286c35
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 12:28:31 2016 -0700

    i965/draw: Use worst-case VBO bounds if brw->num_instances == 0
    
    Previously, we only handled the "I don't know what's going on" case for
    things with InstanceDivisor == 0.  However, in the DrawIndirect case we can
    get num_instances == 0 and we don't know what's going on with the instanced
    ones either.  This commit makes the worst-case bound the default and then
    conservatively tightens the bound.
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8892519751f5a38e12dd64e3fef3976c53eb9e86
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue May 17 21:42:49 2016 -0700

    i965/draw: Delay when we get the bo for vertex buffers
    
    The previous code got the BO the first time we encountered it.  However,
    this can potentially lead to problems if the BO is used for multiple arrays
    with the same buffer object because the range we declare as busy may not be
    quite right.  By delaying the call to intel_bufferobj_buffer, we can ensure
    that we have the full range for the given buffer.
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a01a1eb9e48196a5dde37675c51d294b31c32728
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 11:34:44 2016 -0700

    i965/draw: Stop relying on min_index == -1 for invalid index bounds
    
    The vbo layer passes an index_bounds_valid flag that we should be using
    instead.  This also fixes a bug when min_index == -1 and basevertex != 0
    where we were actually comparing min_index + basevertex == -1 which was
    false and we were getting the wrong buffer-sizing path.
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7011922f1d48357f18af4639fad008f6f33a984
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed May 18 23:47:01 2016 -0700

    vbo: Declare the index range invalid for DrawTransformFeedback
    
    Right now, we're setting the range to [0, 0] which is obviously bogus.
    Instead, we should set it to be invalid like we do for DrawIndirect.
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=df6ec2aba52be66423c90c3f00c599cb2eba4558
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue May 17 22:24:59 2016 -0700

    vbo: Declare the index range invalid for DrawIndirect
    
    Right now, we're just setting the range to [0, MAX_UINT32] which, while
    correct isn't helpful.  With DrawIndirect, you can't really know what the
    actual range is so we may as well flag it as being an invalid range.  This
    is what we do for draws with index buffer which is similar (the indices
    aren't statically known) if a bit simpler.
    
    Cc: "11.1 11.2" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
    Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>