Mesa (master): radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0

[Marek Olšák]

Module: Mesa
Branch: master
Commit: fc4896e686f79893d6496c7a792a6c72cb3759c1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc4896e686f79893d6496c7a792a6c72cb3759c1

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu May 26 20:39:51 2016 +0200

radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0

It's not needed since it was fixed in the kernel.

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

---

 src/gallium/drivers/radeonsi/si_hw_context.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index dcf206d..6221f1c 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -116,8 +116,9 @@ void si_context_gfx_flush(void *context, unsigned flags,
 
 	ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 			SI_CONTEXT_PS_PARTIAL_FLUSH;
-	/* The kernel doesn't flush TC for VI correctly (need TC_WB_ACTION_ENA). */
-	if (ctx->b.chip_class == VI)
+
+	/* DRM 3.1.0 doesn't flush TC for VI correctly. */
+	if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
 		ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
 				SI_CONTEXT_INV_VMEM_L1;