Mesa (master): gallium/radeon: add enum radeon_micro_mode

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 7786f8c63564f1eb421a8636cdbd15c471ec8632
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7786f8c63564f1eb421a8636cdbd15c471ec8632

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Oct 27 01:13:30 2016 +0200

gallium/radeon: add enum radeon_micro_mode

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeon/r600_texture.c  | 10 +++++-----
 src/gallium/drivers/radeon/radeon_winsys.h |  8 ++++++++
 src/gallium/drivers/radeonsi/si_blit.c     |  3 +--
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 7ced41c..6933304 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2347,13 +2347,13 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
 	 */
 	if (rscreen->chip_class >= CIK) {
 		switch (rtex->last_msaa_resolve_target_micro_mode) {
-		case 0: /* displayable */
+		case RADEON_MICRO_MODE_DISPLAY:
 			rtex->surface.tiling_index[0] = 10;
 			break;
-		case 1: /* thin */
+		case RADEON_MICRO_MODE_THIN:
 			rtex->surface.tiling_index[0] = 14;
 			break;
-		case 3: /* rotated */
+		case RADEON_MICRO_MODE_ROTATED:
 			rtex->surface.tiling_index[0] = 28;
 			break;
 		default: /* depth, thick */
@@ -2362,7 +2362,7 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
 		}
 	} else { /* SI */
 		switch (rtex->last_msaa_resolve_target_micro_mode) {
-		case 0: /* displayable */
+		case RADEON_MICRO_MODE_DISPLAY:
 			switch (rtex->surface.bpe) {
 			case 1:
                             rtex->surface.tiling_index[0] = 10;
@@ -2375,7 +2375,7 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
                             break;
 			}
 			break;
-		case 1: /* thin */
+		case RADEON_MICRO_MODE_THIN:
 			switch (rtex->surface.bpe) {
 			case 1:
                                 rtex->surface.tiling_index[0] = 14;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index f65f669..3e30e95 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -263,6 +263,14 @@ enum radeon_surf_mode {
     RADEON_SURF_MODE_2D = 3,
 };
 
+/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
+enum radeon_micro_mode {
+    RADEON_MICRO_MODE_DISPLAY = 0,
+    RADEON_MICRO_MODE_THIN = 1,
+    RADEON_MICRO_MODE_DEPTH = 2,
+    RADEON_MICRO_MODE_ROTATED = 3,
+};
+
 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_SCANOUT                     (1 << 16)
 #define RADEON_SURF_ZBUFFER                     (1 << 17)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 0fd1106..e086ed8 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -22,7 +22,6 @@
  */
 
 #include "si_pipe.h"
-#include "sid.h"
 #include "util/u_format.h"
 #include "util/u_surface.h"
 
@@ -1065,7 +1064,7 @@ resolve_to_temp:
 		      R600_RESOURCE_FLAG_DISABLE_DCC;
 
 	/* The src and dst microtile modes must be the same. */
-	if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
+	if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
 		templ.bind = PIPE_BIND_SCANOUT;
 	else
 		templ.bind = 0;