Mesa (master): isl: Only allow Y-tiling for ASTC textures

[Nanley Chery]

Module: Mesa
Branch: master
Commit: faab6a0f18825bd1bd3a6f0cfc4e4e68e041b6e2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=faab6a0f18825bd1bd3a6f0cfc4e4e68e041b6e2

Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Sep 22 14:51:37 2016 -0700

isl: Only allow Y-tiling for ASTC textures

Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

---

 src/intel/isl/isl_gen7.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index b6a86d2..18687b5 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -215,6 +215,12 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
       *flags &= ~ISL_TILING_W_BIT;
    }
 
+   /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
+    *    If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
+    */
+   if (isl_format_get_layout(info->format)->txc == ISL_TXC_ASTC)
+      *flags &= ISL_TILING_Y0_BIT;
+
    /* MCS buffers are always Y-tiled */
    if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
       *flags &= ISL_TILING_Y0_BIT;