Mesa (master): gallium/radeon: Only convert stencil info if RADEON_SURF_SBUFFER is set

[Michel Dänzer]

Module: Mesa
Branch: master
Commit: 6f844a30c1616eac4955134ff130aad699a8079c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f844a30c1616eac4955134ff130aad699a8079c

Author: Michel Dänzer <michel.daenzer at amd.com>
Date:   Wed Nov  2 19:09:06 2016 +0900

gallium/radeon: Only convert stencil info if RADEON_SURF_SBUFFER is set

Fixes valgrind warnings about using uninitialized memory when starting X.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>

---

 src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 31 +++++++++++++++-------
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index e3eea59..7b85973 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -155,15 +155,20 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
     surf_drm->bankh = surf_ws->bankh;
     surf_drm->mtilea = surf_ws->mtilea;
     surf_drm->tile_split = surf_ws->tile_split;
-    surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
 
     for (i = 0; i <= surf_drm->last_level; i++) {
         surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i], bpe);
-        surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
-                                 &surf_ws->stencil_level[i], bpe);
-
         surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
-        surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
+    }
+
+    if (flags & RADEON_SURF_SBUFFER) {
+        surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
+
+        for (i = 0; i <= surf_drm->last_level; i++) {
+            surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
+                                     &surf_ws->stencil_level[i], bpe);
+            surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
+        }
     }
 }
 
@@ -188,18 +193,24 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
     surf_ws->bankh = surf_drm->bankh;
     surf_ws->mtilea = surf_drm->mtilea;
     surf_ws->tile_split = surf_drm->tile_split;
-    surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
 
     surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
 
     for (i = 0; i <= surf_drm->last_level; i++) {
         surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i],
                                  surf_drm->bpe * surf_drm->nsamples);
-        surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
-                                 &surf_drm->stencil_level[i], surf_drm->nsamples);
-
         surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
-        surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
+    }
+
+    if (surf_ws->flags & RADEON_SURF_SBUFFER) {
+        surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
+
+        for (i = 0; i <= surf_drm->last_level; i++) {
+            surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
+                                     &surf_drm->stencil_level[i],
+                                     surf_drm->nsamples);
+            surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
+        }
     }
 
     set_micro_tile_mode(surf_ws, &ws->info);