Mesa (master): radeonsi: increase MAX_CONTROL_FLOW_DEPTH AKA MaxIfDepth

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 3f6e0063c8e06856004bed9b6bccc2492e351d5a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f6e0063c8e06856004bed9b6bccc2492e351d5a

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Nov  4 12:31:53 2016 +0100

radeonsi: increase MAX_CONTROL_FLOW_DEPTH AKA MaxIfDepth

we don't want to lower deep IFs unconditionally

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_pipe.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 273633c..900de9f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -608,9 +608,8 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
 	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
-		return 16384;
 	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
-		return 32;
+		return 16384;
 	case PIPE_SHADER_CAP_MAX_INPUTS:
 		return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 	case PIPE_SHADER_CAP_MAX_OUTPUTS: