Mesa (master): radeonsi: don' t set vs.epilog.export_prim_id if TES is bound

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d2a56985d7b4b22d176c13d8601f98e18e44d3a1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2a56985d7b4b22d176c13d8601f98e18e44d3a1

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Nov 13 17:30:54 2016 +0100

radeonsi: don't set vs.epilog.export_prim_id if TES is bound

there is no VS epilog in this case

Tested-by: Edmondo Tommasina <edmondo.tommasina at gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_state_shaders.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 9df8f47..72d0518 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -881,10 +881,10 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
 			key->as_ls = 1;
 		else if (sctx->gs_shader.cso)
 			key->as_es = 1;
-
-		if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
-		    sctx->ps_shader.cso->info.uses_primid)
-			key->part.vs.epilog.export_prim_id = 1;
+		else {
+			if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
+				key->part.vs.epilog.export_prim_id = 1;
+		}
 		break;
 	case PIPE_SHADER_TESS_CTRL:
 		key->part.tcs.epilog.prim_mode =