Mesa (master): radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER

[Marek Olšák]

Module: Mesa
Branch: master
Commit: f92113c5a1c1e928a2f50c78866f43eff4cd6630
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f92113c5a1c1e928a2f50c78866f43eff4cd6630

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Oct  1 00:46:39 2016 +0200

radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER

Caches are always flushed at IB boundary.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>

---

 src/gallium/drivers/radeonsi/si_state.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 443dc37..04b57dc 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3414,14 +3414,13 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
 	if (flags & PIPE_BARRIER_FRAMEBUFFER)
 		sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
 
-	if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
-		     PIPE_BARRIER_FRAMEBUFFER |
+	if (flags & (PIPE_BARRIER_FRAMEBUFFER |
 		     PIPE_BARRIER_INDIRECT_BUFFER)) {
 		/* Not sure if INV_GLOBAL_L2 is the best thing here.
 		 *
 		 * We need to make sure that TC L1 & L2 are written back to
-		 * memory, because neither CPU accesses nor CB fetches consider
-		 * TC, but there's no need to invalidate any TC cache lines. */
+		 * memory, because CB fetches don't consider TC, but there's
+		 * no need to invalidate any TC cache lines. */
 		sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
 	}
 }