Mesa (master): i965: use L3 data cache for SSBOs

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: d51c1f9d51ef0e80873a9a32c48606cdce25a209
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d51c1f9d51ef0e80873a9a32c48606cdce25a209

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Mon Sep 26 15:08:52 2016 +0100

i965: use L3 data cache for SSBOs

Anv programs the hardware to use L3 data cache if we use either SSBOs or
images in the shaders, we can program i965 the same way.

gl_shader_program has a bit of a confusing named field with
'NumAtomicBuffers'. It doesn't tell how many buffers are accessed by the
shader in an atomic way but instead the number of atomic counters
manipulated by the shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>

---

 src/mesa/drivers/dri/i965/gen7_l3_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index ad70491..0692b08 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -53,7 +53,8 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
          brw->ctx._Shader->CurrentProgram[stage_states[i]->stage];
       const struct brw_stage_prog_data *prog_data = stage_states[i]->prog_data;
 
-      needs_dc |= (prog && prog->NumAtomicBuffers) ||
+      needs_dc |= (prog && (prog->NumAtomicBuffers ||
+                            prog->NumShaderStorageBlocks)) ||
          (prog_data && (prog_data->total_scratch || prog_data->nr_image_params));
       needs_slm |= prog_data && prog_data->total_shared;
    }