Mesa (master): radeonsi: use TC write-back instead of full cache invalidation

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 40e1f7e09bf1bc9b8ed6f847562bbb7154025420
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=40e1f7e09bf1bc9b8ed6f847562bbb7154025420

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Oct 10 18:51:24 2016 +0200

radeonsi: use TC write-back instead of full cache invalidation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_compute.c    |  2 +-
 src/gallium/drivers/radeonsi/si_state.c      | 12 +++---------
 src/gallium/drivers/radeonsi/si_state_draw.c |  6 +++---
 3 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 632839f..e785106 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -701,7 +701,7 @@ static void si_launch_grid(
 
 		/* The hw doesn't read the indirect buffer via TC L2. */
 		if (r600_resource(info->indirect)->TC_L2_dirty) {
-			sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 			r600_resource(info->indirect)->TC_L2_dirty = false;
 		}
 	}
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 34f3ed7..ad65fc2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3397,21 +3397,15 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
 		 * L1 isn't used.
 		 */
 		if (sctx->screen->b.chip_class <= CIK)
-			sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+			sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 	}
 
 	if (flags & PIPE_BARRIER_FRAMEBUFFER)
 		sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
 
 	if (flags & (PIPE_BARRIER_FRAMEBUFFER |
-		     PIPE_BARRIER_INDIRECT_BUFFER)) {
-		/* Not sure if INV_GLOBAL_L2 is the best thing here.
-		 *
-		 * We need to make sure that TC L1 & L2 are written back to
-		 * memory, because CB fetches don't consider TC, but there's
-		 * no need to invalidate any TC cache lines. */
-		sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
-	}
+		     PIPE_BARRIER_INDIRECT_BUFFER))
+		sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 }
 
 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 33b6b23..c14e852 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1047,18 +1047,18 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 	/* VI reads index buffers through TC L2. */
 	if (info->indexed && sctx->b.chip_class <= CIK &&
 	    r600_resource(ib.buffer)->TC_L2_dirty) {
-		sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+		sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 		r600_resource(ib.buffer)->TC_L2_dirty = false;
 	}
 
 	if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
-		sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+		sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 		r600_resource(info->indirect)->TC_L2_dirty = false;
 	}
 
 	if (info->indirect_params &&
 	    r600_resource(info->indirect_params)->TC_L2_dirty) {
-		sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+		sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 		r600_resource(info->indirect_params)->TC_L2_dirty = false;
 	}