Mesa (master): st/glsl_to_tgsi: remove unnecessary ir_instruction argument from get_opcode

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 15fc74905b64ab41e47d5b50407596ceaeced638
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=15fc74905b64ab41e47d5b50407596ceaeced638

Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date:   Mon Oct 10 11:44:43 2016 +0200

st/glsl_to_tgsi: remove unnecessary ir_instruction argument from get_opcode

Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index be0aa2e..fd2485d 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -527,7 +527,7 @@ public:
                                       st_src_reg src2 = undef_src,
                                       st_src_reg src3 = undef_src);
 
-   unsigned get_opcode(ir_instruction *ir, unsigned op,
+   unsigned get_opcode(unsigned op,
                     st_dst_reg dst,
                     st_src_reg src0, st_src_reg src1);
 
@@ -669,7 +669,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
    int num_reladdr = 0, i, j;
    bool dst_is_64bit[2];
 
-   op = get_opcode(ir, op, dst, src0, src1);
+   op = get_opcode(op, dst, src0, src1);
 
    /* If we have to do relative addressing, we want to load the ARL
     * reg directly for one of the regs, and preload the other reladdr
@@ -900,7 +900,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
  * based on the operands and input opcode, then emits the result.
  */
 unsigned
-glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op,
+glsl_to_tgsi_visitor::get_opcode(unsigned op,
                                  st_dst_reg dst,
                                  st_src_reg src0, st_src_reg src1)
 {