Mesa (master): 29 new commits

Fri Oct 14 22:55:57 UTC 2016

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d65595c0632b0d8036b18553c12fe9fa972e5a2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 22:29:44 2016 -0700

    anv/pipeline: Remove a meta hack from emit_ds_state
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69b2e931d49ff0d0cac1aa39753a447c6d2c059a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 22:14:03 2016 -0700

    anv/image: Create views directly in VkCreate*View
    
    Without meta, we no longer need the _init helpers and the ability to back
    an image view with surface states allocated out of the command buffer.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a2c375af95953e5d36da243457f40d458077f50
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 22:07:04 2016 -0700

    anv/image: Get rid of the usage hacks for meta
    
    Now that meta is gone and we're using blorp, we don't need all of the usage
    hacks.  Instead, the usage provided by the app is exactly the usage that we
    want because the app is the only thing creating image views.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e1a8dd47e1f6fb1849b149a42207b16ffd9c10a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 21:55:34 2016 -0700

    anv: Move Create*Pipelines into genX_cmd_buffer.c
    
    Now that we don't have meta, we have no need for a gen-agnostic pipeline
    create path.  We can, instead, just generate one Create*Pipelines function
    per gen and be done with it.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7df46b7533a0ff257dbdb1b844ce0f4fc1c266ac
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 21:50:31 2016 -0700

    anv/pipeline: Remove support for direct-from-nir shaders
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d557ae4032adafc85a4cb5a76d8653bf0cf6639
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 15:47:45 2016 -0700

    anv: Make entrypoint resolution take a gen_device_info
    
    In order for things such as the ANV_CALL and the ifuncs to work, we used to
    have a singleton gen_device_info structure that got assigned the first time
    you create a device.  Given that the driver will never be used
    simultaneously on two different generations of hardware, this was fairly
    safe to do.  However, it has caused a few hickups and isn't, in general, a
    good plan.  Now that the two primary reasons for this singleton are gone,
    we can get rid of it and make things quite a bit safer.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c9dec80edeb7f1d1774ca51faa806241c1c59cb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 15:41:17 2016 -0700

    anv: Get rid of the ANV_CALL macro
    
    This macro was needed by meta in order to make gen-specific calls from
    gen-agnostic code.  Now that we don't have meta, the remaining two uses are
    fairly trivial to get rid of.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac77528f7d383ee103ed702590f7bc9f05907b61
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 15:29:47 2016 -0700

    anv: Get rid of graphics_pipeline_create_info_extra
    
    Now that we no longer have meta, all pipelines get created via the normal
    Vulkan pipeline creation mechanics.  There is no more need for this bit of
    extra magic data that we've been passing around.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dedc406ec8adc6a36eb2b37e3f565aaa1dce6e3f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 15:06:47 2016 -0700

    anv: Get rid of meta
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d823f92970447859c4891728da4e48f0c9bc0044
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 17:29:36 2016 -0700

    anv: Use blorp for subpass clears
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=51faab487f77e153a9ac05b1e7bca978decc2250
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 14:43:21 2016 -0700

    anv: Use blorp for ClearAttachments
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9eaf12de20ac4143fe79d42018bdbb5a391356f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 19:14:47 2016 -0700

    anv/hiz: Perform HiZ resolves for all partial renders
    
    If we don't, we can end up with corruption in the portion of the depth
    buffer that lies outside the render area when we do a HiZ resolve at the
    end.  The only reason we weren't seeing this before was that all of the
    meta-based clears such as VkCmdClearDepthStencilImage were internally using
    HiZ so the HiZ buffer never truly got out-of-sync.  If the CTS ever tested
    a depth upload (which doesn't care about HiZ) and then a partial render we
    would have seen problems.  Soon, we will be using blorp to do depth clears
    and it won't bother with HiZ so we would get CTS regressions without this.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=58f2315c3819bbd6bab9ee62b0743309feac42cb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 23:35:22 2016 -0700

    anv: Use blorp for ClearDepthStencilImage
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=29e289fa655938f7814bdbb3de7996a8a0f04b60
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Sep 19 15:28:43 2016 -0700

    anv/image: Add an isl_view to anv_image_view
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0340548c8e89d724fe6752fe7a665787c4adf361
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Sep 19 15:14:56 2016 -0700

    anv/image: Rework our handling of 3-D image array ranges
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=146ee31159744941685a3ad04839b125dc0acce4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 11:23:35 2016 -0700

    anv/blorp: Don't hand-roll flush_pipeline_select_3d
    
    When I initially brought up Vulkan blorp, I completely missed that this
    was already factored out.  There's no good reason for us to hand-roll it.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d80c0307eaa91a609f71651fb52122849d35b5ac
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 17:20:00 2016 -0700

    intel/blorp: Add a flag to make blorp not re-emit dept/stencil buffers
    
    In Vulkan, we want to be able to use blorp to perform clears inside of a
    render pass.  If blorp stomps the depth/stencil buffers packets then we'll
    have to re-emit them.  This gets tricky when secondary command buffers get
    involved.  Instead, we'll simply guarantee that the depth and stencil
    buffers we pass to blorp (if any) match those already set in the hardware.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cabf93b80d03ea923cf507218024953b9d0254c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 23:20:12 2016 -0700

    intel/blorp: Add an entrypoint for clearing depth and stencil
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=82a2c49c5f3c8784e5239ebed7ad0bf8a44c687b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Oct 10 09:30:29 2016 -0700

    intel/blorp: Emit a NULL render target for depth/stencil-only operations
    
    This never mattered before because the only time we used blorp
    depth/stencil only was to do HiZ operations on gen6-7.  It may have worked
    in that case (and maybe it didn't) but slow depth clears actually do depth
    rendering so they need a valid render target.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b324c38ae3e47940e5ffe441f169f839a3d53261
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 23:44:57 2016 -0700

    intel/blorp: Allow for running without a PS on gen8+
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=81be7be11960e3edb6968fd5c8d9475f234aae48
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 17:17:05 2016 -0700

    intel/blorp: Add an "enabled" bit to surface_info
    
    This gives a slightly smarter way to check whether or not a particular
    surface exists than looking at the address.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc4bb5a7e302569f593882feabff1379b640022a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 23:08:08 2016 -0700

    intel/blorp: Emit more complete DEPTH_STENCIL state
    
    This should now set the pipeline up properly for doing depth and/or stencil
    clears by plumbing through depth/stencil test values.  We are now also
    emitting color calculator state for blorp operations without an actual
    shader because that is where the stencil reference value goes pre-SKL.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7017742ad726e5d396027223f7a9fcf6f9fa1807
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 22:33:32 2016 -0700

    intel/blorp: Unify the DEPTH_STENCIL emit code across gens
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf2e3c3163d9702588d71f130024128d59ca5c17
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 17:04:10 2016 -0700

    intel/blorp: Simplify depth/stencil config
    
    The newly reworked depth/stencil config code can properly handle having
    depth, stencil, both, or neither.  We no longer need to predicate it on
    having depth or stencil.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0414aaa1339f26bffef3852ea1030c339dded314
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Oct 10 09:29:34 2016 -0700

    intel/blorp: Set QPitch for depth and HiZ on gen8+

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=563fa63bf2245e84584efb1143ea5acd7374df46
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 22:10:34 2016 -0700

    intel/blorp: Add support for binding an actual stencil buffer
    
    While we're here, we also make depth without HiZ work.
    
    v2:
     - Use the correct surface type for 1-D on SKL+
     - Set QPitch on BDW+
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f180faab79edc713a203cf5596257613b81741b3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri Oct 7 16:58:34 2016 -0700

    intel/blorp: Move CLEAR_PARAMS setup into emit_depth_stencil_config
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1fcf1a957430cc794ab55a7edea046df2a60517
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 22:13:57 2016 -0700

    intel/genxml: Add a uint MOCS field to 3DSTATE_STENCIL_BUFFER
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5dacd3caee9ff41055bd974ae1e4ba40cb2f5984
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct 6 22:03:12 2016 -0700

    intel/blorp: Make the Z component of the primitive adjustable
    
    We want to be able to start doing slow depth clears with blorp.  This
    allows us to adjust the depth we're clearing to.
    
    Signed-off-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>