Mesa (master): radeonsi: set VGT_GS_ONCHIP_CNTL on CIK and later

[Marek Olšák]

Module: Mesa
Branch: master
Commit: e24dc4316487eeaa6ee8aa5c709546d814e96f03
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e24dc4316487eeaa6ee8aa5c709546d814e96f03

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Oct 25 21:47:52 2016 +0200

radeonsi: set VGT_GS_ONCHIP_CNTL on CIK and later

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Cc: 11.2 12.0 13.0  <mesa-stable at lists.freedesktop.org>

---

 src/gallium/drivers/radeonsi/si_state.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 42689da..0633b64 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3925,6 +3925,14 @@ static void si_init_config(struct si_context *sctx)
 	si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
 
 	if (sctx->b.chip_class >= CIK) {
+		/* If this is 0, Bonaire can hang even if GS isn't being used.
+		 * Other chips are unaffected. These are suboptimal values,
+		 * but we don't use on-chip GS.
+		 */
+		si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
+			       S_028A44_ES_VERTS_PER_SUBGRP(64) |
+			       S_028A44_GS_PRIMS_PER_SUBGRP(4));
+
 		si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
 		si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
 		si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));