Mesa (master): radeonsi: fix broken texture filtering on SI-CIK since GFX9 changes

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 0fb5a505fac7be0a1831b565019f0f04369e56bd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fb5a505fac7be0a1831b565019f0f04369e56bd

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Apr  3 00:22:16 2017 +0200

radeonsi: fix broken texture filtering on SI-CIK since GFX9 changes

Don't clear state[7] on SI-CIK, and only do the meta stuff on VI+.
Fixes: 5abf60076ce4 ("radeonsi/gfx9: image descriptor changes in mutable fields")

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100531
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 32 ++++++++++++++-------------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 2b911585a6..8f5a16ba47 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -404,26 +404,28 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 		va += base_level_info->offset;
 	}
 
-	if (vi_dcc_enabled(tex, first_level)) {
-		meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
-			  tex->dcc_offset;
-
-		if (sscreen->b.chip_class <= VI)
-			meta_va += base_level_info->dcc_offset;
-	} else if (tex->tc_compatible_htile && !is_stencil) {
-		meta_va = tex->htile_buffer->gpu_address;
-	}
-
 	state[0] = va >> 8;
 	state[1] &= C_008F14_BASE_ADDRESS_HI;
 	state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
-	state[6] &= C_008F28_COMPRESSION_EN;
-	state[7] = 0;
+	if (sscreen->b.chip_class >= VI) {
+		state[6] &= C_008F28_COMPRESSION_EN;
+		state[7] = 0;
 
-	if (meta_va) {
-		state[6] |= S_008F28_COMPRESSION_EN(1);
-		state[7] = meta_va >> 8;
+		if (vi_dcc_enabled(tex, first_level)) {
+			meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
+				  tex->dcc_offset;
+
+			if (sscreen->b.chip_class <= VI)
+				meta_va += base_level_info->dcc_offset;
+		} else if (tex->tc_compatible_htile && !is_stencil) {
+			meta_va = tex->htile_buffer->gpu_address;
+		}
+
+		if (meta_va) {
+			state[6] |= S_008F28_COMPRESSION_EN(1);
+			state[7] = meta_va >> 8;
+		}
 	}
 
 	if (sscreen->b.chip_class >= GFX9) {