Mesa (master): radeonsi: set up HTILE in descriptors only when level 0 is accessible

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 94965b8219508954a5fddd74e7c6de4503cd9931
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=94965b8219508954a5fddd74e7c6de4503cd9931

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Jul 30 16:41:39 2017 +0200

radeonsi: set up HTILE in descriptors only when level 0 is accessible

Compression isn't enabled with non-zero levels.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 18b070ba3a..b080562348 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -432,7 +432,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 
 			if (sscreen->b.chip_class <= VI)
 				meta_va += base_level_info->dcc_offset;
-		} else if (tex->tc_compatible_htile) {
+		} else if (tex->tc_compatible_htile && first_level == 0) {
 			meta_va = tex->resource.gpu_address + tex->htile_offset;
 		}