Mesa (master): i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
Kenneth Graunke
kwg at kemper.freedesktop.org
Wed Aug 2 17:01:46 UTC 2017
Module: Mesa
Branch: master
Commit: 595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jul 31 22:04:25 2017 -0700
i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/intel_blit.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index eca8736804..b1db7aa229 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -187,7 +187,6 @@ get_blit_intratile_offset_el(const struct brw_context *brw,
* The offsets we get from ISL in the tiled case are already aligned.
* In the linear case, we need to do some of our own aligning.
*/
- assert(mt->surf.row_pitch % 64 == 0);
uint32_t delta = *base_address_offset & 63;
assert(delta % mt->cpp == 0);
*base_address_offset -= delta;
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