Mesa (17.2): 22 new commits
Emil Velikov
evelikov at kemper.freedesktop.org
Mon Aug 7 11:51:29 UTC 2017
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=29df4deef2743f0474902a4e467bac76b5403adf
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Aug 7 12:45:40 2017 +0100
Update version to 17.2.0-rc3
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4371d14f17049e4878966de60cfb88e8cd137cb
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Mon Jul 31 11:27:23 2017 -0700
anv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b2c034f6457ef62cc20d308a91620116cdc057d
Author: Tomasz Figa <tfiga at chromium.org>
Date: Sun Jul 30 00:02:46 2017 +0900
st/dri: enable 32-bit RGBX/RGBA formats only on Android
X/GLX can't handle them. This removes almost 500 GLX visuals that were
incorrectly exposed.
This is a less invasive version of Marek's .getCapability series.
Note: the patch is not applicable for master, but only for the 17.2
branch.
Suggested-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Tomasz Figa <tfiga at chromium.org>
CC: <mesa-stable at lists.freedesktop.org>
Fixes: f33d8af7aa354d "st/dri: add 32-bit RGBX/RGBA formats"
[Emil Velikov: commit message polish]
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4e163094d9e4a0515adc695553d8af34be379fd
Author: Tim Rowley <timothy.o.rowley at intel.com>
Date: Mon Jul 31 16:59:06 2017 -0500
swr/rast: fix scons gen_knobs.h dependency
Copy/paste error was duplicating a gen_knobs.cpp rule.
Fixes: 5079c277b57 ("swr: [scons] Fix windows build")
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
(cherry picked from commit e4a6ae06cf01a21d7fe32e3ff2fc441102d68f82)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a181e6244db1ac4ad1a098f485bdfc151db5325
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Mon Jul 31 22:48:27 2017 +1000
mesa/st: fix conditional jump depends on uninitialised value
Reported by valgrind at:
glsl_to_tgsi_visitor::visit(ir_expression*) (st_glsl_to_tgsi.cpp:1560)
When compiling the Deus Ex shaders.
Fixes: 28a5e7104 ("st/glsl_to_tgsi: handle precise modifier")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Reviewed-by: Karol Herbst <karolherbst at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 06237fc9e15e6274c24f89985a224135a617a491)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ef9fe7229d44ce222d77029e02326c92f068f55
Author: Scott D Phillips <scott.d.phillips at intel.com>
Date: Fri Jun 30 13:49:53 2017 -0700
gles: Restore some lost typedefs
GLES/gl.h has historically provided some typedefs that are not
used in the API itself. Restore these typedefs that were lost to
avoid breaking applications.
These seem to be the only typedefs removed in the update.
Fixes: 7fd0817 "Update Khronos-supplied headers"
[Eric: added a big warning to revert this patch when pulling the updated header]
Signed-off-by: Eric Engestrom <eric.engestrom at imgtec.com>
(cherry picked from commit 3db05ed1d10738d0c2f14cb692d5d618c5872dcd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f872e62c2dbd4ad522f87c858393ccaa507ca8e
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 31 08:37:10 2017 +0100
Revert "st_glsl_to_tgsi: rewrite rename registers to use array fully."
This reverts commit 3008161d28e38336ba39aba4769a2deaf9732f55,
which caused a regression for VMWare.
The initial code had some recursion in it, that I removed by accident
trying to add back the recursion broke lots of things, take the high
road and revert for now.
Fixes: 3008161d (st_glsl_to_tgsi: rewrite rename registers to use array fully.)
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit b8bea9a0506cc312f4b32762d73598a8a220cf08)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5fac38cedfb919d6dfa3e0760b2a6d4384db72a
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 27 21:52:20 2017 +0100
radv: handle 10-bit format clamping workaround.
This fixes:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.*
for a2r10g10b10 formats as destination on SI/CIK hardware.
This adds support to the meta program for emitting 10-bit
outputs, and adds 10-bit support to the fragment shader key.
It also only does the int8/10 on SI/CIK.
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit df61a05019d5c7479d4b29d251af4231f125e61c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=579ecfd91e3c3320e17c8a2709bdc35d813bb61f
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sun Jul 30 23:26:11 2017 +0200
radv: Don't underflow non-visible VRAM size.
In some APU situations the reported visible size can be larger than
VRAM size. This properly clamps the value.
Surprisingly both CTS and spec seem to allow a heap type with size 0,
so this seemed like the easiest option to me.
Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
Fixes: 4ae84efbc5c "radv: Use enum for memory heaps."
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
(cherry picked from commit 8229706ad86b27ed571f17872006a488fcd35378)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b279b32718cc6e0397a368269d3ad52fd685aad
Author: Bruce Cherniak <bruce.cherniak at intel.com>
Date: Wed Aug 2 18:14:19 2017 -0500
st/osmesa: add osmesa framebuffer iface hash table per st manager
Commit bbc29393d3 didn't include osmesa state_tracker. This patch adds
necessary initialization.
Fixes crash in OSMesa initialization.
Created-by: Charmaine Lee <charmainel at vmware.com>
Tested-by: Bruce Cherniak <bruce.cherniak at intel.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Cc: 17.2 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 9966c85e01a4344d2a6bb76e432e0bed70d52ff6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6efb8d79a9aa33c6b2ac61c1544ef1a9e12f3d8b
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 3 13:48:40 2017 +1000
intel/vec4/gs: reset nr_pull_param if DUAL_INSTANCED compile failed.
If dual object compile fails (as seems to happen with virgl a
fair bit, and does piglit even have any tests for it?), we end up
not restarting the pull params, so we call
vec4_visitor::move_uniform_array_access_to_pull_constant
a second time and it runs over the ends of the alloc.
Fixes: tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test
running inside virgl on ivybridge.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 271fa3a684ef0eefe99087c13d1abb099784163f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=795b712bd7f455fddd8779ac75f038392cec510c
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Mon Jul 31 10:56:15 2017 +0100
i965/blit: Remember to include miptree buffer offset in relocs
Remember to add the offset to the start of the buffer in the relocation
or else we write 0xff into random bytes elsewhere.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit fb63c43fd1b7adb5cb4f34e7616e7d564ca178e5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=43a2b178c294b054c932687bdc0b5bb8303529a9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jul 31 22:04:25 2017 -0700
i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
(cherry picked from commit 595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5def4f5a97d3ebdc5f1d34f8c03259510229a53
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Jul 12 11:36:29 2017 -0700
spirv: Fix SpvImageFormatR16ui
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: "17.1 17.2" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 95c6a97464e7baaca6e09f829da0be5ac8c50297)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2a60ff20a8248aa5d8d5949e8f433c97b3a3506
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Thu Jun 22 09:24:34 2017 +0200
dri3: Wait for all pending swapbuffers to be scheduled before touching the front
This implements a wait for glXWaitGL, glXCopySubBuffer, dri flush_front and
creation of fake front until all pending SwapBuffers have been committed to
hardware. Among other things this fixes piglit glx-copy-sub-buffers on dri3.
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Cc: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 185ef06fd2db782d9d3d6046580f7cece02c4797)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c8673d42035e79da6879f7204d48abecb4b67ff
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Jul 27 14:06:59 2017 +0200
gallium/radeon: fix ARB_query_buffer_object conversion to boolean
The issue here is that the immediate is treated as a 64-bit value,
and fetching it does not work reliably with swizzles that are different
from xy and zw.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit da83687c4ba7e9022f6f14176393a9e3c6391ed5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=381ccaa1cbff41a8626f0bf3ac5fe90500598226
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Aug 1 05:10:49 2017 +0100
radeon/ac: use ds_swizzle for derivs on si/cik.
This looks like it's supported since llvm 3.9 at least,
so switch over radeonsi and radv to using it, -pro also
uses this. We can now drop creating lds for these operations
as the ds_swizzle operation doesn't actually write to lds at all.
Acked-by: Marek Olšák <marek.olsak at amd.com>
(stable requested due to fixing radv CIK conformance tests)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit cb6f16dce90b4737f62588f8ea5083ee6544787e)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2dd6030fbb0d8f94f1dbba3c73aa87cf6f38781c
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Mon Jul 31 18:28:45 2017 -0700
ac/nir: fix lsb emission
This makes it match radeonsi. The LLVM backend itself will emit the
correct instruction, but LLVM might do incorrect optimizations since it
thinks the output is undefined when the input is 0, even though it's not
supposed to be. We really need a new intrinsic, or for the backend to
become smarter and recognize this pattern.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <basni at google.com>
(cherry picked from commit 6d731c5651ea98551e0bf0c1a8896d5ea63558d5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a90d99f7a5f091c2f5697dd7b11d9803f369aa3a
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Mon Jul 31 18:26:49 2017 -0700
nir: fix algebraic optimizations
The optimizations are only valid for 32-bit integers. They were
mistakenly firing for 64-bit integers as well.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit de914615753678c5514733a37ac7d0360a43e525)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6806773905e0a3654ebd0d2a963a706bb70f0a64
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jul 31 16:53:19 2017 +0200
Revert "st/mesa: release sampler views when redefining a texture in st_context_teximage"
This reverts commit 5c1241268ba9b240cb79ab9a30c5255b176c83c9.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101961
Cc: 17.2 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit d85802e501a67e193a4a363cfe3b4c17c3d9e2e9)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e872f4b5352521f2cb4d9abd840988a30db483d
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Sat Jul 29 09:17:53 2017 +0200
radeonsi: ensure that temp array allocas are in the entry block
Otherwise, code generation fails. This has become necessary since some
shaders are wrapped in control flow.
Fixes: 081ac6e5c6d2 ("radeonsi/gfx9: always wrap GS and TCS in an if-block (v2)")
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 2879a602dd5d133c792d262b6be98aa6f810c16d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21ea75b3e93843e4f36b082c54780fc23d128111
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Jul 25 21:39:20 2017 +0200
mesa: fix mismatch when returning 64-bit bindless uniform handles
The slower convert-and-copy process performs a bad conversion
because it converts the value to signed 64-bit integer, but
bindless uniform handles are considered unsigned 64-bit.
This fixes "Check glUniform*() with mixed texture units/handles"
from arb_bindless_texture-uniform piglit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Cc: "17.2" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit b38c9c57f272b54a190be4efd4297effa1a3deab)
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