Mesa (master): 25 new commits

Mon Aug 21 21:05:26 UTC 2017

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a98b1a8922fa6990d0ab677770fc8ab6c9286a4b
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Aug 2 23:20:00 2017 -0700

    i965: Optimize reading the destination type
    
    brw_hw_type_to_reg_type() needs to know only whether the file is
    BRW_IMMEDIATE_VALUE or not, which is not a valid file for the
    destination. gcc and clang will evaluate __builtin_strcmp() at compile
    time, so we can use it to pass a constant file for the destination.
    
       text	   data	    bss	    dec	    hex	filename
    7816214	 346248	 420496	8582958	 82f72e	i965_dri.so before
    7816070	 346248	 420496	8582814	 82f69e	i965_dri.so after
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=91ef9490549567968a51bd8c68ebb60e47ebcdcb
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Aug 2 23:20:39 2017 -0700

    i965: Mark brw_hw_type_to_reg_type() as a pure function
    
       text	   data	    bss	    dec	    hex	filename
    7816886	 346248	 420496	8583630	 82f9ce	i965_dri.so before
    7816214	 346248	 420496	8582958	 82f72e	i965_dri.so after
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e07fe890353dce5fbefb0e03856f7faabfac06cb
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 21:13:03 2017 -0700

    i965: Hide the register type hardware encodings
    
    So we stop mixing them with the logical enum.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fab67a4415cbc577a8f94d4b5f7668bec6df5e1
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 21:08:20 2017 -0700

    i965: Stop using hardware register types directly
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c746f1c88820485afbf62774120d58ddd317f508
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Aug 2 13:41:32 2017 -0700

    i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.c
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a2471b5014f5ecc6b96a1a9c228f9ee3d0fdb98
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 17:31:36 2017 -0700

    i965: Move brw_reg_type_letters() as well
    
    And add "to_" to the name for consistency with the other functions in
    this file.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cb0a7941b27d368bc973d22b3a4db091a1852e4
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 17:59:10 2017 -0700

    i965: Switch to using the logical register types
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb2cd462b1c66b9bace4d061bf4ff960419e83d9
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 16:51:58 2017 -0700

    i965: Add functions to abstract access to register types
    
    Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions
    provided access to the hardware encodings for the register types. We
    often mixed these with the logical BRW_REGISTER_TYPE_* enums (which
    themselves used to be the hardware format!) with bad results.
    
    With that functionality now available with the hw_ versions (see
    previous commit), we now add functions that take the logical
    BRW_REGISTER_TYPE_* enums and convert into the hardware format and vice
    versa. To do the conversion we also have to provide the file.
    
    Note the asymmetry between the two functions: the new getter reads the
    file from the instruction word, and to ensure that is always set the
    setter writes both the file and the type.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fb8323328684bd7fe4e8c71c7415f51acf25e5b
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 14:25:54 2017 -0700

    i965: Rename brw_inst's functions that access the register type
    
    Put hw_ in the name so that it's clear these are the hardware encodings.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e379af492f0f4c05061b8251e7cf18ed438056c
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 16:56:10 2017 -0700

    i965: Index brw_hw_reg_type_to_size()'s table by logical type
    
    I'll be transitioning everything to use the logical types.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1ac1a3d257460c2706e91ff933679d7c8889294
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 17:50:22 2017 -0700

    i965: Add a brw_hw_type_to_reg_type() function
    
    Will be used in later commits.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbe7dd13dd46657da7fdd864c916d9d6b08c96bb
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 17:50:05 2017 -0700

    i965: Use a common table to translate logical to hardware types
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfcc9aa829438675aed9d9e227d88d325932efe0
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 11:08:11 2017 -0700

    i965: Extract functions dealing with register types to separate file
    
    I'm going to encapsulate all of the logic dealing with register types in
    this file.
    
    Rename the parameters for the hardware encodings from type -> hw_type at
    the same time.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=890f863da072bceeb5fdeba504873059e2e0353b
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 26 17:03:12 2017 -0700

    i965: Reverse file/type arguments to register type functions
    
    I think of the initial arguments as "state" and the last as the actual
    subject.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=92f787ff86abc588939878f43fa898bc2b069342
Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Jul 25 14:25:27 2017 -0700

    i965: Add support for disassembling 64-bit integer immediates
    
    After the last patch converted things into enums, I helpfully got a
    compiler warning about these missing from the switch statement.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=deae25ce3783a770f2e4e8f73f935656791121ae
Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Jul 25 14:05:44 2017 -0700

    i965: Use separate enums for register vs immediate types
    
    The hardware encodings often mean different things depending on whether
    the source is an immediate.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8815b9677ff70723ee55f2e567d50c1d4e9762b3
Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Jul 25 13:16:25 2017 -0700

    i965: Reorder brw_reg_type enum values
    
    These vaguely corresponded to the hardware encodings, but that is purely
    historical at this point. Reorder them so we stop making things "almost
    work" when mixing enums.
    
    The ordering has been closen so that no enum value is the same as a
    compatible hardware encoding.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce6b8627d87f14e15f2f4bbc6034b32c34557cb3
Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Jul 27 18:29:50 2017 -0700

    i965: Validate destination restrictions with vector immediates
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d79c828d80f289de51b12efc2a5448fe7ebafd6
Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Aug 1 12:21:54 2017 -0700

    i965: Don't let raw-move check be tricked by immediate vector types
    
    UB and B type encodings are the same as UV and VF. Noticed when writing
    the following patch.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=48aa6ecb8759fcaed68db4b03600c92572759158
Author: Matt Turner <mattst88 at gmail.com>
Date:   Tue Aug 1 10:12:56 2017 -0700

    i965: Only change type of 0.0f to VF if destination stride == 1
    
    The destination stride must be equivalent to a dword if VF is used.
    
    Also, since the only compaction table entires with "i:vf" have the
    destination as "r:f" specifically check that the destination is of type
    float.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=56a676eed289bdea928b56e7533023f775468bb2
Author: Matt Turner <mattst88 at gmail.com>
Date:   Mon Jul 31 19:13:15 2017 -0700

    i965: Remove CONT/BREAK from instruction compaction test
    
    These cannot be compacted. A similar mistake was fixed in commit
    90eaf01616a8
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d661e60625492a0e9f7931856c7e97e2eb7ef50
Author: Matt Turner <mattst88 at gmail.com>
Date:   Mon Jul 31 19:07:42 2017 -0700

    i965: Test instruction compaction on all supported Gens
    
    Note that there's no point in testing on G45, since its compaction is
    the same as Gen5. Same logic applies to Gen7 variants and low-power
    parts.
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ff7d9b85312cdfe986dcfded4aac157f441494f
Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Aug 2 16:17:05 2017 -0700

    i965: Silence signed/unsigned comparison warning
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eac89911e5fa7129d053418677df32d7ff6e0372
Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Jul 27 18:30:14 2017 -0700

    i965: Move compaction "prepass" into brw_eu_compact.c
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=17641f638839e09a8fbfafc3f889b0696a4bf99a
Author: Matt Turner <mattst88 at gmail.com>
Date:   Mon Jul 31 15:35:49 2017 -0700

    i965: Mark src inst pointer const in compaction code
    
    Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>