Mesa (master): radeon/vcn: correct target buffer pitch calculation

[Leo Liu]

Module: Mesa
Branch: master
Commit: df6c087a383f801c32352309e9b858340989955d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=df6c087a383f801c32352309e9b858340989955d

Author: Leo Liu <leo.liu at amd.com>
Date:   Mon Aug 21 11:50:38 2017 -0400

radeon/vcn: correct target buffer pitch calculation

since the way should be as same as UVD

Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>

---

 src/gallium/drivers/radeon/radeon_vcn_dec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index a60b969a27..51391627d5 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -631,7 +631,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
 	decode->db_pitch = align(dec->base.width, 32);
 	decode->db_surf_tile_config = 0;
 
-	decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.bpe;;
+	decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
 	decode->dt_uv_pitch = decode->dt_pitch / 2;
 
 	decode->dt_tiling_mode = 0;