Mesa (master): 27 new commits
Alejandro Pinheiro
apinheiro at kemper.freedesktop.org
Wed Dec 6 08:05:23 UTC 2017
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1e257a5bfaa0e1b3bbfd9846311b8f419d4c626
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Mon Jul 24 22:42:59 2017 +0200
i965/fs: Use untyped_surface_read for 16-bit load_ssbo
SSBO loads were using byte_scattered read messages as they allow
reading 16-bit size components. byte_scattered messages can only
operate one component at a time so we needed to emit as many messages
as components.
But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the
untyped_surface_read message to read pairs of 16-bit components using only
one message. Once each pair is read it is unshuffled to return the proper
16-bit components. vec3 case is assimilated to vec4 but the 4th component
is ignored.
16-bit scalars are read using one byte_scattered_read message.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Rework optimization using unshuffle 16 reads (Chema Casanova)
v3: Use W and D types insead of HF and F in shuffle to avoid rounding
erros (Jason Ekstrand)
Use untyped_surface_read for 16-bit vec3. (Jason Ekstrand)
v4: Use subscript insead of chaging type and stride (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce2e572c4c1b1f16e0b68923713001651b3f9bca
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Wed Jul 12 14:49:41 2017 +0200
i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg
Currently, we use byte-scattered write messages for storing 16-bit
into an SSBO. This is because untyped surface messages have a fixed
32-bit size.
This patch optimizes these 16-bit writes by combining 2 values (e.g,
two consecutive components aligned with 32-bits) into a 32-bit register,
packing the two 16-bit words.
16-bit single component values will continue to use byte-scattered
write messages. The same will happens when the first consecutive
component is not aligned 32-bits.
This optimization reduces the number of SEND messages used for storing
16-bit values potentially by 2 or 4, which cuts down execution time
significantly because byte-scattered writes are an expensive
operation as they only write a component for message.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Rework optimization using shuffle 16 write and enable writes
of 16bit vec4 with only one message of 32-bits. (Chema Casanova)
v3: - Fix coding style (Eduardo Lima)
- Reorganize code to avoid duplication. (Jason Ekstrand)
- Include new comments to explain the length calculations to
fix alignment issues of components. (Jason Ekstrand)
- Fix issues with writemask yz with 16-bit writes. (Jason Ektrand)
v4: (Jason Ekstrand)
- Reorganize 64-bit ssbo-writes to avoid using slots_per_component.
- Comment about why suffle is needed when using byte_scattered_write.
Signed-off-by: Eduardo Lima <elima at igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66ce6ce78f4eeb0a103e35b6c819e7269b4bd3e1
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:32:17 2017 +0200
anv: Enable SPV_KHR_16bit_storage and VK_KHR_16bit_storage for SSBO/UBO
Enables SPV_KHR_16bit_storage on gen 8+.
VK_KHR_16bit_storage is enabled for SSBO/UBO using the
VK_KHR_get_physical_device_properties2 functionality to expose
if the extension is supported or not.
v2: update due rebase against master (Alejandro)
v3: (Jason Ekstrand)
- Move this patch up in VK_KHR_16bit_storage series enabling only
storageBuffer16BitAccess and uniformAndStorageBuffer16BitAccess.
- Only expose VK_KHR_16bit_storage on Gen8+
v4: (Jason Ekstrand)
- Squash enable SPV_KHR_16bit_storage into VK_KHR_16bit_storage
enablement for SSBO/UBO.
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Signed-off-by: Eduardo Lima Mitev <elima at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3282309f74e72991635bfde08f5e5e58a18604c7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Nov 21 00:03:46 2017 +0100
i965/fs: Enables 16-bit load_ubo with sampler
load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit
surface format defined. So when reading 16-bit components with the
sampler we need to unshuffle two 16-bit components from each 32-bit
component.
Using the sampler avoids the use of the byte_scattered_read message
that needs one message for each component and is supposed to be
slower.
v2: (Jason Ekstrand)
- Simplify component selection and unshuffling for different bitsizes
- Remove SKL optimization of reading only two 32-bit components when
reading 16-bits types.
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3db31c0b06acf2d1505070434764c89bc58a48af
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Mon Nov 20 23:10:51 2017 +0100
i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit components
This helpers are used to load/store 16-bit types from/to 32-bit
components.
The functions shuffle_32bit_load_result_to_16bit_data and
shuffle_16bit_data_for_32bit_write are implemented in a similar
way than the analogous functions for handling 64-bit types.
v1: Explain need of temporary in shuffle operations. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa4a9d63bba57245bd9552990c92b48a9ed89b16
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 08:20:07 2017 +0200
i965/fs: Use byte scattered read for 16-bit load_ssbo
Used to enable 16-bit reads at do_untyped_vector_read, that is used on
the following intrinsics:
* nir_intrinsic_load_shared
* nir_intrinsic_load_ssbo
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: - Add bitsize to scattered read operation (Jason Ekstrand)
- Remove implementation of 16-bit UBO read from this patch.
- Avoid assertion at opt_algebraic caused by ADD of two IMM with
offset with BRW_REGISTER_TYPE_UD type found on matrix tests.
(Jose Maria Casanova)
v4: (Jason Ekstrand)
- Put if case for 16-bits at the beginning of the if ladder.
- Use type_sz(dest.type) * 8 as bit_size parameter for scattered read.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c57a3f200dd50e345a9983e5ae950091e6241af6
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 08:19:17 2017 +0200
i965/fs: Add byte scattered read message and fs support
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_read.
v3: (Jason Ekstrand)
- Use renamed brw_byte_scattered_data_element_from_bit_size method
- Assert scattered read for Gen8+ and Haswell.
- Use conditional expresion at components_read.
- Include comment about params for scattered opcodes.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4031bdfa927fb4c3c5d0bdadc70634f3c1a5eac
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 29 16:10:02 2017 +0200
i965/fs: Predicate byte scattered writes if needed
While on Untyped Surface messages the bits of the execution mask are
ANDed with the corresponding bits of the Pixel/Sample Mask, that is
not the case for byte scattered writes. That is needed to avoid ssbo
stores writing on helper invocations. So when that can affect, we load
the sample mask, and predicate the send message.
Note: the need for this patch was tested with a custom test. Right now
the 16 bit storage CTS tests doesnt need this path in order to get a
full pass.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96f1926aab96a92e45f1dec226390aae46d3ea45
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:17:09 2017 +0200
i965/fs: Use byte_scattered_write on 16-bit store_ssbo
We need to rely on byte scattered writes as untyped writes are 32-bit
size. We could try to keep using 32-bit messages when we have two or
four 16-bit elements, but for simplicity sake, we use the same message
for any component number. We revisit this aproach in the follwing
patches.
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: (Jason Ekstrand)
- Include bit_size to scattered write message and remove namespace
- specific for scattered messages.
- Move comment to proper place.
- Squashed with i965/fs: Adjust type_size/type_slots on store_ssbo.
(Jose Maria Casanova)
- Take into account that get_nir_src returns now WORD types for
16-bit sources instead of DWORD.
v4: (Jason Ekstrand)
- Rename lenght variable to num_components.
- Include assertions before emit_untyped_write.
- Remove type_slot in favor of num_slot and first_slot.
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1a9936ee1c7d2abe641eb785786c908c5ed799c
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 08:16:01 2017 +0200
i965/fs: Add byte scattered write message and fs support
v2: (Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_write.
v3: - Remove leftover newline (Topi Pohjolainen)
- Rename brw_data_size to brw_scattered_data_element and use
defines instead of an enum (Jason Ekstrand)
- Assert scattered write for Gen8+ and Haswell (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d038deaa400c819e5867d1e417849b124ccd07b3
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:14:56 2017 +0200
i965/fs: Add remove_extra_rounding_modes optimization
Although from SPIR-V point of view, rounding modes are attached to the
operation/destination, on i965 it is a status, so we don't need to
explicitly set the rounding mode if the one we want is already set.
Taking into account that the default mode is RTE, one possible
optimization would be optimize out the first RTE set for each
block. For in order to work, we would need to take into account block
interrelationships. At this point, it is not worth to complicate the
optimization for such small gain.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
v3: Reset optimization for every block. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=82fa4d45e7f25f6773d4487ae93feebcf6183eeb
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:14:09 2017 +0200
i965/fs: Enable rounding mode on f2f16 ops
By default we don't set the rounding mode. We only set
round-to-near-even or round-to-zero mode if explicitly set from nir.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
v3: Use new helper brw_rnd_mode_from_nir_op (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6cd14f2131a5b1c41ab777ef3ea041993de1c1b
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:12:59 2017 +0200
i965/fs: Define new shader opcode to set rounding modes
Although it is possible to emit them directly as AND/OR on brw_fs_nir,
having a specific opcode makes it easier to remove duplicate settings
later.
v2: (Curro)
- Set thread control to 'switch' when using the control register
- Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode.
- Avoid magic numbers setting rounding mode field at control register.
v3: (Curro)
- Remove redundant and add missing whitespace lines.
- Match printing instruction to IR opcode "rnd_mode"
v4: (Topi Pohjolainen)
- Fix code style.
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac8d4734f695b718ae072c2ad961a2cc546b21e0
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 08:11:58 2017 +0200
i965: Add support for control register
Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.
From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
subsection "Control Register" (page 754):
"Subregister cr0.0:ud contains normal operation control fields such as the
floating-point mode ... "
Floating-point Rounding mode is changed at bits 5:4 of cr0.0:
"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
00b = Round to Nearest or Even (RTNE)
01b = Round Up, toward +inf (RU)
10b = Round Down, toward -inf (RD)
11b = Round Toward Zero (RTZ)"
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d5ee507fb4a385f98ba19bd901ce4e3aca7def4
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:11:05 2017 +0200
i965/fs: Handle 32-bit to 16-bit conversions
Conversions to 16-bit need having aligment between the 16-bit
and 32-bit types. So the conversion operations unpack 16-bit types
to with an stride=2 and then applies a MOV with the conversion.
v2 (Jason Ekstrand):
- Avoid the general use of stride=2 for 16-bit register types.
v3 (Topi Pohjolainen)
- Code style fix
(Jason Ekstrand)
- Now nir_op_f2f16 was renamed to nir_op_f2f16_undef
because conversion to f16 with undefined rounding is explicit
Signed-off-by: Eduardo Lima <elima at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a05b6f25bf4bfad7bb56d20aca0d2424607f9004
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:08:20 2017 +0200
i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type
Note that we don't remove the assert at i965/vec4. At this point half
float support is only for the scalar backend.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75a88d85671e03f6913dcc8bd288515e8ee8a99b
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 08:06:45 2017 +0200
i965: Support for 16-bit base types in helper functions
v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand)
v3: Fix coding style (Topi Pohjolainen)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Eduardo Lima <elima at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d28ca70005968c7becb4e598b97e72c8e4890a2
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Jul 1 08:06:17 2017 +0200
i965/vec4: Handle 16-bit types at type_size_xvec4
These types have similar vec4 sizes as their 32-bit counterparts.
The vec4 backend doesn't support 16-bit types and probably never will,
but this method is called by the scalar backend at
fs_visitor::nir_setup_outputs(), so we still need to provide valid vec4
sizes for 16-bit types. In the future, something different should be
implemented to avoid this dependency.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4049c041221e614c64641fcbeb5b396fd3daa507
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sat Jul 1 08:02:45 2017 +0200
spirv/nir: Add support for SPV_KHR_16bit_storage
v2: Minor changes after rebase against recent master (Alejandro
Pinheiro)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0667a8bd8029936aed5b97b5ceef7c58526e53c
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 08:05:55 2017 +0200
spirv: Enable FPRoundingMode decorator to nir operations
SpvOpFConvert now manages the FPRoundingMode decorator for the
returning values enabling the nir_rounding_mode in the conversion
operation to fp16 values.
v2: Fixed breaking of specialization constants. (Jason Ekstrand)
v3: Avoid nir_rounding_mode * casting. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=549894a681cce2c96006b740a10a36c005d05d0b
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sat Jul 1 08:04:40 2017 +0200
spirv/nir: Handle 16-bit types
v2: Added more missing implementations of 16-bit types. (Jason Ekstrand)
v3: Store values in values[0].u16[i] (Jason Ekstrand)
Include switches based on bitsize for 16-bit types
(Chema Casanova)
v4: Coding style fixes (Jason Ekstrand)
Use vtn_u64_literal and u64[0] at 64-bit SpvOpConstant (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Eduardo Lima <elima at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f440d00d2b6ae6f74fb850ea5acec1f1b5efa58
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 07:58:26 2017 +0200
nir: Handle fp16 rounding modes at nir_type_conversion_op
nir_type_conversion enables new operations to handle rounding modes to
convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
and nir_op_f2f16_rtz.
The undefined behaviour doesn't has any effect and uses the original
nir_op_f2f16 operation.
v2: Indentation fixed (Jason Ekstrand)
v3: Use explicit case for undefined rounding and assert if
rounding mode is used for non 16-bit float conversions
(Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2af63683bc61e1efb8f634697770d314ef07c882
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sat Jul 1 08:01:21 2017 +0200
nir: Populate conversion opcodes to 16-bit types
This will include the following NIR ALU opcodes:
* nir_op_i2i16
* nir_op_i2f16
* nir_op_u2u16
* nir_op_u2f16
* nir_op_f2i16
* nir_op_f2u16
* nir_op_f2f16
v2: Remove "from" 16-bit in commit subject (Topi Pohjolainen)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7114454305a64f9624d7b1fcc726d97d7f1835a
Author: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Date: Sat Jul 1 07:56:51 2017 +0200
nir: Add rounding modes enum
v2: Added comments describing each of the rounding modes. (Jason
Ekstrand)
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5165e222d15a546a550a3165dce05eac81f94482
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sat Jul 1 07:54:50 2017 +0200
nir: Add support for 16-bit types (half float, int16 and uint16)
v2: Renamed glsl_half_float_type() to glsl_float16_t_type().
(Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Eduardo Lima <elima at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52b10c7f20cf1613e47d5320339e61029549c420
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Aug 17 09:51:22 2017 +0200
mesa/st: Handle 16-bit types at st_glsl_storage_type_size()
This is basically to avoid "not handle in switch" warnings.
v2: Let the new types hit the assertion instead. (Marek Olšák
and Jason Ekstrand)
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59f458cd8703b97b31b826499f01fcc9a30cd606
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sat Jul 1 07:46:41 2017 +0200
glsl: Add 16-bit types
Adds new INT16, UINT16 and FLOAT16 base types.
The corresponding GL types for half floats were reused from the
AMD_gpu_shader_half_float extension. The int16 and uint16 types come from
NV_gpu_shader_5 extension.
This adds the builtins and the lexer support.
To avoid a bunch of warnings due to cases not handled in switch, the
new types have been added to a few places using same behavior as
their 32-bit counterparts, except for a few trivial cases where they are
already handled properly. Subsequent patches in this set will provide
correct 16-bit implementations when needed.
v2: * Use FLOAT16 instead of HALF_FLOAT as name of the base type.
* Removed float16_t from builtin types.
* Don't copy 16-bit types as if they were 32-bit values in
copy_constant_to_storage().
* Use get_scalar_type() instead of adding a new custom switch
statement.
(Jason Ekstrand)
v3: Use GL_FLOAT16_NV instead of GL_HALF_FLOAT for consistency
(Ilia Mirkin)
v4: Add missing 16-bit base types support in glsl_to_nir (Eduardo Lima).
v5: Fix coding style (Topi Poholainen).
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova at igalia.com>
Signed-off-by: Eduardo Lima <elima at igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro at igalia.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
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