Mesa (master): radv: always emit all compute block components

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 97e57740d852aee282d5902de5a63c32071473da
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=97e57740d852aee282d5902de5a63c32071473da

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Dec 14 12:51:06 2017 +0100

radv: always emit all compute block components

The number of grid components is always 3 when gl_NumWorkGroups
is declared, because it relies on the number of components of
nir_instrinsic_load_num_work_groups.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c  |  9 ++++++---
 src/amd/vulkan/radv_cmd_buffer.c | 15 +++++----------
 2 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f3602a267d..ce25e57eba 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -745,8 +745,10 @@ static void create_function(struct nir_to_llvm_context *ctx,
 	switch (stage) {
 	case MESA_SHADER_COMPUTE:
 		radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets);
-		if (ctx->shader_info->info.cs.grid_components_used)
-			add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */
+		if (ctx->shader_info->info.cs.grid_components_used) {
+			add_user_sgpr_argument(&args, ctx->ac.v3i32,
+					       &ctx->num_work_groups);
+		}
 		add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
 		add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
 		add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
@@ -950,7 +952,8 @@ static void create_function(struct nir_to_llvm_context *ctx,
 	switch (stage) {
 	case MESA_SHADER_COMPUTE:
 		if (ctx->shader_info->info.cs.grid_components_used) {
-			set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, &user_sgpr_idx, ctx->shader_info->info.cs.grid_components_used);
+			set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE,
+						     &user_sgpr_idx, 3);
 		}
 		break;
 	case MESA_SHADER_VERTEX:
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 68371dbbe7..e68c5a4038 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3487,9 +3487,6 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
 	struct radeon_winsys_cs *cs = cmd_buffer->cs;
 	struct ac_userdata_info *loc;
 	unsigned dispatch_initiator;
-	uint8_t grid_used;
-
-	grid_used = compute_shader->info.info.cs.grid_components_used;
 
 	loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
 				    AC_UD_CS_GRID_SIZE);
@@ -3514,7 +3511,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
 		radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
 
 		if (loc->sgpr_idx != -1) {
-			for (unsigned i = 0; i < grid_used; ++i) {
+			for (unsigned i = 0; i < 3; ++i) {
 				radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 				radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 						COPY_DATA_DST_SEL(COPY_DATA_REG));
@@ -3581,15 +3578,13 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
 
 		if (loc->sgpr_idx != -1) {
 			assert(!loc->indirect);
-			assert(loc->num_sgprs == grid_used);
+			assert(loc->num_sgprs == 3);
 
 			radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
-						  loc->sgpr_idx * 4, grid_used);
+						  loc->sgpr_idx * 4, 3);
 			radeon_emit(cs, blocks[0]);
-			if (grid_used > 1)
-				radeon_emit(cs, blocks[1]);
-			if (grid_used > 2)
-				radeon_emit(cs, blocks[2]);
+			radeon_emit(cs, blocks[1]);
+			radeon_emit(cs, blocks[2]);
 		}
 
 		radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |