Mesa (master): anv: Improve flushing around STATE_BASE_ADDRESS

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 92128590bc78bcbbfb19144c7004b31d6405bbcb
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=92128590bc78bcbbfb19144c7004b31d6405bbcb

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Jan 30 19:53:17 2017 -0800

anv: Improve flushing around STATE_BASE_ADDRESS

It is not clear from the docs exactly how pipelined STATE_BASE_ADDRESS
actually is.  We know from experimentation that we need to flush the
render cache prior to emitting STATE_BASE_ADDRESS and invalidate the
texture cache afterwards.  The only thing the PRM says is that, on gen8+
we're supposed to invalidate the state cache after STATE_BASE_ADDRESS
but experimentation has indicated that doing so does nothing whatsoever.

Since we don't really know, let's do just a bit more flushing in the
hopes that this won't be a problem again.  In particular:

 1) Do a CS stall before we emit STATE_BASE_ADDRESS since we don't
    really know whether or not it's pipelined.

 2) Do a data cache flush in case what runs before STATE_BASE_ADDRESS
    is a compute shader.

 3) Invalidate the state and constant caches after STATE_BASE_ADDRESS
    because the state may be getting cached there (we don't really know).

Reported-by: Mark Janes <mark.a.janes at intel.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>

---

 src/intel/vulkan/genX_cmd_buffer.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index d0e76e3d..0ad7cd5 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -63,7 +63,9 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
     * clear depth, reset state base address, and then go render stuff.
     */
    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+      pc.DCFlushEnable = true;
       pc.RenderTargetCacheFlushEnable = true;
+      pc.CommandStreamerStallEnable = true;
    }
 
    anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
@@ -145,6 +147,8 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
     */
    anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
       pc.TextureCacheInvalidationEnable = true;
+      pc.ConstantCacheInvalidationEnable = true;
+      pc.StateCacheInvalidationEnable = true;
    }
 }