Mesa (master): nvc0: expose int64
Ilia Mirkin
imirkin at kemper.freedesktop.org
Thu Feb 9 18:06:06 UTC 2017
Module: Mesa
Branch: master
Commit: 1e4f5988edd2fb9eafcf5010498b0e93bae1ae26
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e4f5988edd2fb9eafcf5010498b0e93bae1ae26
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Feb 5 13:08:07 2017 -0500
nvc0: expose int64
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
docs/features.txt | 2 +-
docs/relnotes/17.1.0.html | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 9ac0272..5905dba 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -283,7 +283,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_ARB_ES3_2_compatibility DONE (i965/gen8+)
GL_ARB_fragment_shader_interlock not started
GL_ARB_gl_spirv not started
- GL_ARB_gpu_shader_int64 DONE (i965/gen8+, radeonsi, softpipe, llvmpipe)
+ GL_ARB_gpu_shader_int64 DONE (i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe)
GL_ARB_indirect_parameters DONE (nvc0, radeonsi)
GL_ARB_parallel_shader_compile not started, but Chia-I Wu did some related work in 2014
GL_ARB_pipeline_statistics_query DONE (i965, nvc0, radeonsi, softpipe, swr)
diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
index 57a5ca8..6a0dae4 100644
--- a/docs/relnotes/17.1.0.html
+++ b/docs/relnotes/17.1.0.html
@@ -44,7 +44,7 @@ Note: some of the new features are only available with certain drivers.
</p>
<ul>
-<li>GL_ARB_gpu_shader_int64 on i965/gen8+, radeonsi, softpipe, llvmpipe</li>
+<li>GL_ARB_gpu_shader_int64 on i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe</li>
</ul>
<h2>Bug fixes</h2>
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index e99dc4c..30efac8 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -244,6 +244,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
case PIPE_CAP_DOUBLES:
+ case PIPE_CAP_INT64:
return 1;
case PIPE_CAP_COMPUTE:
return (class_3d < GP100_3D_CLASS);
@@ -281,7 +282,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
- case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
return 0;
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