Mesa (master): vec4: use DIM instruction when loading DF immediates in HSW

[Samuel Iglesias Gonsálvez]

Module: Mesa
Branch: master
Commit: 301fdfd8387856ea83c0ac0bff95915c0872c2f4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=301fdfd8387856ea83c0ac0bff95915c0872c2f4

Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date:   Wed Dec  7 10:32:38 2016 +0100

vec4: use DIM instruction when loading DF immediates in HSW

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 065e317..98e023a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1208,6 +1208,15 @@ vec4_visitor::setup_imm_df(double v)
    if (devinfo->gen >= 8)
       return brw_imm_df(v);
 
+   /* gen7.5 does not support DF immediates straighforward but the DIM
+    * instruction allows to set the 64-bit immediate value.
+    */
+   if (devinfo->is_haswell) {
+      dst_reg dst = retype(dst_reg(VGRF, alloc.allocate(2)), BRW_REGISTER_TYPE_DF);
+      emit(DIM(dst, brw_imm_df(v)))->force_writemask_all = true;
+      return swizzle(src_reg(retype(dst, BRW_REGISTER_TYPE_DF)), BRW_SWIZZLE_XXXX);
+   }
+
    /* gen7 does not support DF immediates */
    union {
       double d;