Mesa (17.0): 34 new commits
Emil Velikov
evelikov at kemper.freedesktop.org
Wed Jan 25 13:28:00 UTC 2017
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d283ec0a7b61bc33d970f5cb4c2bfbd63d255c2c
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Jan 25 13:24:27 2017 +0000
Update version to 17.0.0-rc2
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9577977266068b1b3666e0265bd0d6dcb1563572
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Jan 17 12:00:37 2017 +0200
i965/blorp: Make post draw flush more explicit
Blits do not need any special treatment as the target buffer
object is added to render cache just as one does for normal draw.
Color clears and resolves in turn require explicit "end of pipe
synchronization". It is not clear what this means exactly but the
assumption is that render cache flush with command stream stall
should be sufficient.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 180653c357d19ca88f7895f59874a58fac99cc53)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8621961d4334bbfd51cb9e1934c6dcbc741699a9
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Jan 17 11:48:49 2017 +0200
i965/gen6: Issue direct depth stall and flush after depth clear
instead of calling unconditionally brw_emit_mi_flush() which
does:
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_CS_STALL);
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE);
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 46b346899d98e29943f8cd74c25bcb8d2f868a49)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d5a98f106b0695aca305bac8eb8833324bb8fe3
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Jan 17 11:44:52 2017 +0200
i965: Make depth clear flushing more explicit
Current blorp logic issues unconditional "flush everything"
(see brw_emit_mi_flush()) after each render. For example, all
blits issue this unconditionally which shouldn't be needed if
they set render cache properly so that subsequent renders do
necessary flushing before drawing.
In case of piglit:
ext_framebuffer_multisample-accuracy all_samples depth_draw small
intel_hiz_exec() is always preceded by blorb blit and the
unconditional flush looks to hide the lack of stall and flushes
in depth clears. By removing the brw_emit_mi_flush() I get gpu
hangs.
This patch adds the stalls and flushes mandated by the spec
and gets rid of those hangs.
v2 (Jason, Ken): Document the rational for separating
depth cache flush and stall on Gen7.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit e6da6943fed1228c551af1f0e1a405b6d67b41ae)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e6445caa96f66736b47b257a59dc922e31b7cf6
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Jan 17 11:04:22 2017 +0200
i965/blorp: Use the render cache mechanism instead of explicit flushing
by replacing brw_emit_mi_flush() with brw_render_cache_set_check_flush().
The latter splits the flush in two:
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_CS_STALL);
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE);
instead of
int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (brw->gen >= 6) {
flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_VF_CACHE_INVALIDATE |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CS_STALL;
}
brw_emit_pipe_control_flush(brw, flags);
v2 (Jason): Check that destination exists before trying to add to
render cache. Depth clears and resolves don't have it.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 4840a53e902b0f2b9841d9dbb90e479a3688153d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e405d0d3c653dc00049e2c713dbc158014055529
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jan 20 01:13:39 2017 +0100
radeonsi: always set the TCL1_ACTION_ENA when invalidating L2
Some CIK-VI docs say this is the default behavior on SI. That doesn't
answer whether it's also the default behavior on CIK-VI.
Cc: 17.0 13.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
(cherry picked from commit 573bf0940a08e18a511e338de478f30fd95a1590)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c4b8c75e2df340db306a5193eb6bc03babfd8c1
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Mon Jan 23 23:16:42 2017 +0200
radv: don't resubmit the same cs over and over while tracing
Fixes: 97dfff54 ("radv: Dump command buffer on hang.")
Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
CC: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit f65b3641c3233f1697b96ea8126b578dae6de4f1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e35cfa15cf2aa894dd267309eed250f6bc3c68c6
Author: George Kyriazis <george.kyriazis at intel.com>
Date: Wed Jan 18 17:09:08 2017 -0600
swr: Align query results allocation
Some query results struct contents are declared as cache line aligned.
Use aligned malloc, and align the whole struct, to be safe.
Fixes crash when compiling with clang.
CC: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak at intel.com>
(cherry picked from commit 00847e4f14dd237dfcdb2c3d15be1325a08ccf5a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34f902e17efb2f3265d5629f387fdc9a8f08091d
Author: Bruce Cherniak <bruce.cherniak at intel.com>
Date: Thu Jan 19 15:44:52 2017 -0600
swr: Prune empty nodes in CalculateProcessorTopology.
CalculateProcessorTopology tries to figure out system topology by
parsing /proc/cpuinfo to determine the number of threads, cores, and
NUMA nodes. There are some architectures where the "physical id" begins
with 1 rather than 0, which was creating and empty "0" node and causing a
crash in CreateThreadPool.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97102
Reviewed-By: George Kyriazis <george.kyriazis at intel.com>
CC: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit b829206b0739925501bcc68233437d6d03b79795)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4cf4690d1b20a8eab7296c79051ad05a9a5cc25
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Jan 16 16:43:54 2017 +0100
st/glsl_to_tgsi: use DDIV instead of DRCP + DMUL
Fixes GL45-CTS.gpu_shader_fp64.built_in_functions.
v2: use DDIV unconditionally (Roland)
Reviewed-by: Roland Scheidegger <sroland at vmware.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak at amd.com> (v1)
Tested-by: Glenn Kennard <glenn.kennard at gmail.com>
Tested-by: James Harvey <lothmordor at gmail.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit cfabbbcfd778cc404813c9f05a9ef79efe531980)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f6c6b910156629f988277ef0c177a2e97ca17e0
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Jan 16 16:39:06 2017 +0100
glsl: split DIV_TO_MUL_RCP into single- and double-precision flags
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Tested-by: Glenn Kennard <glenn.kennard at gmail.com>
Tested-by: James Harvey <lothmordor at gmail.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit b71c415c3d288da4b5f533ece42f50f4f20a8c33)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23ead4c7b22aaf60f1a902fbea268b57b88d3a78
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Jan 19 14:44:57 2017 +0100
r600: implement DDIV
Tested-by: Glenn Kennard <glenn.kennard at gmail.com>
Tested-by: James Harvey <lothmordor at gmail.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit e4f8f9a638c1ffb9b76840b088290f11f0f91813)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7856dfdbabbb08678471c89c0dbddd6e730499d1
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Jan 19 14:44:24 2017 +0100
r600: factor out cayman_emit_unary_double_raw
We will use it for DDIV.
Tested-by: Glenn Kennard <glenn.kennard at gmail.com>
Tested-by: James Harvey <lothmordor at gmail.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 488560cfe6ee2206f7a7f894694ebc43b419be61)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41b93b1fe047ebdaae7cc4d644633412cee81c35
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Thu Jan 19 14:38:54 2017 +0100
r600: double multiply can handle only one multiply at a time
It seems clear that trying to multiply two pairs of doubles would result
in the temporary register getting overwritten by the second pair. So
make the code more explicit.
Tested-by: Glenn Kennard <glenn.kennard at gmail.com>
Tested-by: James Harvey <lothmordor at gmail.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 76b02d2fe1df5351f67f53d07b37952043f0a84c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8857256214a34cabcf2444b3839b1a928242faa5
Author: Rob Clark <robdclark at gmail.com>
Date: Sun Jan 22 13:38:43 2017 -0500
freedreno/a5xx: set frag shader threadsize
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 31daeb5bf14334bc0d39f28c9102cd15d834abfc)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=516b34908d576eb91157de1722cc3748538af891
Author: Rob Clark <robdclark at gmail.com>
Date: Sun Jan 22 12:23:27 2017 -0500
freedreno/a5xx: set fragcoordxy properly
What a3xx docs call IJPERSPCENTERREGID.. the xy coord passed into
bary.f. We were incorrectly setting both this and gl_FragCoord.xy to
the same register resulting in all sorts of hilarity.
Fixes stk, vdrift, 0ad, probably a bunch others.
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 8d6af93e76bb9e592293b632b22b2b756cc0cae8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0645c0e0d4f8e10d6e178e420405f707644dfdbc
Author: Rob Clark <robdclark at gmail.com>
Date: Mon Jan 16 14:02:54 2017 -0500
freedreno/a5xx: fix psize
Note spritelist (POINTLIST_PSIZE) seems not to be a thing anymore on
a5xx.
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 6cc93bedc15d09395ab6a92a0a129d06a8cd8ae8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6aade42111304a8c79fe515bbe3286631bd70d37
Author: Rob Clark <robdclark at gmail.com>
Date: Sun Jan 15 13:19:47 2017 -0500
freedreno/a5xx: srgb fix
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 141a4f86d6b9c0c4dbde511b741576a103f8f7ff)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dc6ed53c1a8431a818d2f13e60f340d60f80127
Author: Rob Clark <robdclark at gmail.com>
Date: Sun Jan 15 08:43:44 2017 -0500
freedreno/a5xx: fix int vbos
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 69fbb458cf59fbab5f6675ad256a266b04d54700)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfe14ab39c4277e89c5d38ae11f82d86852b5473
Author: Rob Clark <robdclark at gmail.com>
Date: Sat Jan 14 07:59:42 2017 -0500
freedreno/a5xx: fix clear for uint/sint formats
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 16671e970444f154ffa60d2aaadee4d065eb6103)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=250b1cad3bd233a3d74753eb5a42df24ed1efa09
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Jan 11 11:31:40 2017 -0500
freedreno/a5xx: fix cull state
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 4d9aa4f67d6316feea93901bf29b76a68c4333cd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9318d81574bc87b61f7b5104cd7070baa9cd51e4
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Jan 11 11:30:21 2017 -0500
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 4c39458460075f6c1ea9e4607769513b96c6dd82)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=00cdbfe6efa84d5f6f4293980f79cc94002c64f5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jan 19 11:28:31 2017 -0800
nir/search: Use the correct bit size for integer comparisons
The previous code always compared integers as 64-bit. Due to variations
in sign-extension in the code generated by nir_opt_algebraic.py, this
meant that nir_search doesn't always do what you want. Instead, 32-bit
values should be matched as 32-bit and 64-bit values should be matched
as 64-bit. While we're here we unify the unsigned and signed paths.
Now that we're using the right bit size, they should be the same since
the only difference we had before was sign extension.
This gets the UE4 bitfield_extract optimization working again. It had
stopped working due to the constant 0xff00ff00 getting sign-extended
when it shouldn't have.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Cc: "17.0 13.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit bb96b034616d9d099752efb005b5c05e8644059c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=83deab2f6aaeccffba200528637456d38abe3af2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jan 20 12:27:34 2017 -0800
intel/blorp/copy: Properly handle clear colors for CCS_E images
In order to handle CCS_E, we stomp the image format to a UINT format and
then do some bitcasting logic in the shader. This works fine since SKL
render compression only considers the channel layout of the format and
not the format itself. In order for this to work on images that have
been fast-cleared, we need to also convert the clear color so that, when
interpreted as UINT, it provides the same bit value as it would have in
the original format. This fixes a bunch of OpenGL ES CTS tests for
copy_image when we start using CCS more aggressively.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 817f9e3b17c784cbe40639a4b370edc762bd2513)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de2dfa1dc39d18904b6aaf339872ed3ebf9cba87
Author: Andres Rodriguez <andresx7 at gmail.com>
Date: Wed Jan 18 17:48:36 2017 -0500
radv: fix include order for installed headers v2
In situations where libdrm_amdgpu and mesa are installed to the same
location, the mesa installed headers will take precedence over the git
source headers.
This is due to the AMDGPU_CFLAGS containing the install directory.
This situation can cause build errors if the git version of a header is
newer than the currently installed version of a header (e.g. git pull
updates vulkan.h)
Note: using the same install prefix for mesa and libdrm is probably a
common occurrence since it is described in the radeonBuildHowTo wiki:
https://www.x.org/wiki/radeonBuildHowTo/
v2: added sign-off
Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit a3ad6a34c6ba222ec93a2cfd0cac205c62574eb7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c2951c7f94b303cabd32aa92e9469315b926b6e
Author: Andres Rodriguez <andresx7 at gmail.com>
Date: Wed Jan 18 18:07:56 2017 -0500
vulkan/wsi: clarify the severity of lack of DRI3 v2
The current message sounds like a small warning, clarify that it can
result in lack of presentation support and application crashes.
v2: add "if they do" (Bas)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98263
Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
Acked-by: Jason ekstrand <jason at jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit e0674e740bf84085dec898ffd87bdeb2027e620f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3bfa959a836eae4460c4640158d01d4257c883a
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Jan 19 16:20:00 2017 +0000
anv: don't require render target isl bit for depth/stencil surfaces
Blorp can deal with depth/stencil surfaces blits/copies without the
render target requirement. Also having both render target and
depth/stencil requirement is incompatible from isl's point of view.
This fixes an image creation issue in the high level quality settings
of the Unity3D player, which requires a depth texture with src/dst
transfer & 4x multisampling.
v2: Simply aspect checking condition (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Cc: 13.0 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 74c23bde5b8155a84233265c56bedac8f38de14e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a259b800df1cc5e7023c4233bf04f703a4571445
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Fri Jan 13 16:08:28 2017 +0000
spirv: don't assert with location decorations on non i/o variables
Some applications might add location decoration to samplers. Rather
than raising an error it seems it would make more sense to just
discard these decorations.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 8a28e764d0e28d0d4dfa3b81b89fa3baf30e94f2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45f13c2be08f014581a0099f5ce8db79ff9e2142
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Jan 20 01:19:49 2017 +0100
gallium/hud: add missing break in hud_cpufreq_graph_install()
Fixes: e99b9395bef "gallium/hud: Add support for CPU frequency monitoring"
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 383fc8e9f340e80695aca2cd585957af0e081eb9)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b72f8de873be316cd4267547722c07b1cf0f1254
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jan 18 22:15:35 2017 +0100
radeonsi: don't forget to add HTILE to the buffer list for texturing
This fixes VM faults. Discovered by Samuel Pitoiset.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98975
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99450
Cc: 17.0 13.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor at folklore1984.net>
(cherry picked from commit e490b7812cae778c61004971d86dc8299b6cd240)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cc5774e5e7b268017af9527c1e1af1185c9745a
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Wed Jan 18 09:28:47 2017 +0100
radeonsi: fix texture gather on stencil textures
At least on VI, texture gather doesn't work with a 24_8 data format, so
use 8_8_8_8 and a modified swizzle instead.
A bit of background: When creating a GL_STENCIL_INDEX8 texture, we select
the X24S8 pipe format because we don't support stencil-only render targets
properly. With mip-mapping this can lead to a setup where the tiling is
incompatible with stencil texturing, and a flushed stencil texture is
used. For the flushed stencil, a literal X24S8 is used because there were
issues with an 8bpp DB->CB copy.
Longer term, it would be good if we could get away from these workarounds,
i.e. properly support an S8 format for stencil-only rendering and flushed
stencil. Since stencil texturing is somewhat rare, it's not a high
priority.
Fixes GL45-CTS.texture_cube_map_array.sampling.
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Acked-by: Edward O'Callaghan <funfunctor at folklore1984.net>
(cherry picked from commit 3cd092c41508dde2e6259f09df1736911a828548)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=50a607cf70073d5980b07f73f38bd991b68f7029
Author: Zachary Michaels <zmichaels at oblong.com>
Date: Thu Jan 19 10:50:16 2017 +0100
radeonsi: Always leave poly_offset in a valid state
This commit makes si_update_poly_offset set poly_offset to NULL if
uses_poly_offset is false. This way poly_offset either points into the
currently queued rasterizer, or it is NULL.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99451
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
(cherry picked from commit d7d32b3bfe86bd89d94d59393907bce1cb9dab7c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=613154fc8fee89c3791c174363832581ab871580
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Jan 16 12:13:50 2017 +0100
mesa/main: fix meta caller of _mesa_ClampColor
Since _mesa_ClampColor properly checks for support of the API function
now, it's meta callers need to check support as well.
Fixes: 963311b71f ("mesa/main: fix version/extension checks in _mesa_ClampColor")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99401
Tested-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit a7c635ec6589f600f0d52d0097774ea0b938de9f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff81869f0dcd2210e5f09c2e0e0c116f46952734
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jan 19 14:39:10 2017 +1000
gallivm: use #ifdef not #if for PIPE_ARCH_BIG_ENDIAN
This fixes the build on ppc/s390.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit ef71b867ee152d8161a8c7320e89843801236249)
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