Mesa (master): gallium: enable int64 on radeonsi, llvmpipe, softpipe

Nicolai Hähnle nh at kemper.freedesktop.org
Fri Jan 27 09:22:38 UTC 2017


Module: Mesa
Branch: master
Commit: c5e76a262a4246267bbbfa803aebeeb733388e11
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c5e76a262a4246267bbbfa803aebeeb733388e11

Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date:   Tue Jan 24 21:22:32 2017 +0100

gallium: enable int64 on radeonsi, llvmpipe, softpipe

All of these have had support for the TGSI opcodes since before most of
the glsl compiler work landed.

Also update the docs accordingly, including the missing note about i965.

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

---

 docs/features.txt                        |  2 +-
 docs/relnotes/17.1.0.html                | 61 ++++++++++++++++++++++++++++++++
 src/gallium/drivers/llvmpipe/lp_screen.c |  2 +-
 src/gallium/drivers/radeonsi/si_pipe.c   |  4 +--
 src/gallium/drivers/softpipe/sp_screen.c |  2 +-
 5 files changed, 66 insertions(+), 5 deletions(-)

diff --git a/docs/features.txt b/docs/features.txt
index aff0016..55b1fbb 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -283,7 +283,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
   GL_ARB_ES3_2_compatibility                            DONE (i965/gen8+)
   GL_ARB_fragment_shader_interlock                      not started
   GL_ARB_gl_spirv                                       not started
-  GL_ARB_gpu_shader_int64                               started (airlied for core and Gallium, idr for i965)
+  GL_ARB_gpu_shader_int64                               DONE (i965/gen8+, radeonsi, softpipe, llvmpipe)
   GL_ARB_indirect_parameters                            DONE (nvc0, radeonsi)
   GL_ARB_parallel_shader_compile                        not started, but Chia-I Wu did some related work in 2014
   GL_ARB_pipeline_statistics_query                      DONE (i965, nvc0, radeonsi, softpipe, swr)
diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html
new file mode 100644
index 0000000..1b5535b
--- /dev/null
+++ b/docs/relnotes/17.1.0.html
@@ -0,0 +1,61 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
+<html lang="en">
+<head>
+  <meta http-equiv="content-type" content="text/html; charset=utf-8">
+  <title>Mesa Release Notes</title>
+  <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+  <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 17.1.0 Release Notes / TBD</h1>
+
+<p>
+Mesa 17.1.0 is a new development release.
+People who are concerned with stability and reliability should stick
+with a previous release or wait for Mesa 17.1.1.
+</p>
+<p>
+Mesa 17.1.0 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+
+<h2>SHA256 checksums</h2>
+<pre>
+TBD.
+</pre>
+
+
+<h2>New features</h2>
+
+<p>
+Note: some of the new features are only available with certain drivers.
+</p>
+
+<ul>
+<li>GL_ARB_gpu_shader_int64 on i965/gen8+, radeonsi, softpipe, llvmpipe</li>
+</ul>
+
+<h2>Bug fixes</h2>
+
+<ul>
+</ul>
+
+<h2>Changes</h2>
+
+TBD.
+
+</div>
+</body>
+</html>
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 6ef22b8..0982c35 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -267,6 +267,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return 1;
    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+   case PIPE_CAP_INT64:
       return 1;
 
    case PIPE_CAP_VENDOR_ID:
@@ -343,7 +344,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_TGSI_FS_FBFETCH:
    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
-   case PIPE_CAP_INT64:
       return 0;
    }
    /* should only get here on unhandled cases */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 9f3cd05..1fe8b9f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -413,7 +413,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_CULL_DISTANCE:
 	case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 	case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
-        case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
+	case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
+	case PIPE_CAP_INT64:
 		return 1;
 
 	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -466,7 +467,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_NATIVE_FENCE_FD:
 	case PIPE_CAP_TGSI_FS_FBFETCH:
 	case PIPE_CAP_TGSI_MUL_ZERO_WINS:
-	case PIPE_CAP_INT64:
 		return 0;
 
 	case PIPE_CAP_QUERY_BUFFER_OBJECT:
diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c
index f5216b0..ec530a4 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -165,6 +165,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+   case PIPE_CAP_INT64:
       return 1;
    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
       return 16;
@@ -293,7 +294,6 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_TGSI_FS_FBFETCH:
    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
-   case PIPE_CAP_INT64:
       return 0;
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
       return 4;




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