Mesa (master): radeonsi: also prefetch compute shaders

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 4a4ff66dbebe836492a6b6321742c21ca9bcd70a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a4ff66dbebe836492a6b6321742c21ca9bcd70a

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Jan 24 03:41:05 2017 +0100

radeonsi: also prefetch compute shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_compute.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index fe29fb1..d05c488 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -372,6 +372,18 @@ static bool si_switch_compute_shader(struct si_context *sctx,
 			      RADEON_PRIO_SCRATCH_BUFFER);
 	}
 
+	/* Prefetch the compute shader to TC L2.
+	 *
+	 * We should also prefetch graphics shaders if a compute dispatch was
+	 * the last command, and the compute shader if a draw call was the last
+	 * command. However, that would add more complexity and we're likely
+	 * to get a shader state change in that case anyway.
+	 */
+	if (sctx->b.chip_class >= CIK) {
+		cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b,
+					 0, program->shader.bo->b.b.width0);
+	}
+
 	shader_va = shader->bo->gpu_address + offset;
 	if (program->use_code_object_v2) {
 		/* Shader code is placed after the amd_kernel_code_t