Mesa (master): gallium/radeon: enable suballocations for VRAM with no CPU access

[Marek Olšák]

Module: Mesa
Branch: master
Commit: d4fac1e1d7f7c43663d64e826e946f6da2da7a73
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4fac1e1d7f7c43663d64e826e946f6da2da7a73

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Jun 29 18:33:05 2017 +0200

gallium/radeon: enable suballocations for VRAM with no CPU access

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeon/r600_buffer_common.c |  4 +++-
 src/gallium/drivers/radeon/radeon_winsys.h      | 15 ++++++++++++---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c       |  3 +++
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c   |  3 +++
 4 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 262fe1db83..4bf293daf2 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -176,8 +176,10 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
 	 */
 	if (!rscreen->info.has_dedicated_vram &&
 	    (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
-	    res->domains == RADEON_DOMAIN_VRAM)
+	    res->domains == RADEON_DOMAIN_VRAM) {
 		res->domains = RADEON_DOMAIN_VRAM_GTT;
+		res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
+	}
 
 	if (rscreen->debug_flags & DBG_NO_WC)
 		res->flags &= ~RADEON_FLAG_GTT_WC;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 95543bb208..4ecd73f01d 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -659,6 +659,7 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
 }
 
 enum radeon_heap {
+    RADEON_HEAP_VRAM_NO_CPU_ACCESS,
     RADEON_HEAP_VRAM,
     RADEON_HEAP_VRAM_GTT, /* combined heaps */
     RADEON_HEAP_GTT_WC,
@@ -669,6 +670,7 @@ enum radeon_heap {
 static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
 {
     switch (heap) {
+    case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
     case RADEON_HEAP_VRAM:
         return RADEON_DOMAIN_VRAM;
     case RADEON_HEAP_VRAM_GTT:
@@ -685,6 +687,8 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
 static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
 {
     switch (heap) {
+    case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+        return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
     case RADEON_HEAP_VRAM:
     case RADEON_HEAP_VRAM_GTT:
     case RADEON_HEAP_GTT_WC:
@@ -701,14 +705,19 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
 {
     /* VRAM implies WC (write combining) */
     assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+    /* NO_CPU_ACCESS implies VRAM only. */
+    assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
 
-    /* Unsupported flags: NO_CPU_ACCESS, NO_SUBALLOC, SPARSE. */
-    if (flags & ~RADEON_FLAG_GTT_WC)
+    /* Unsupported flags: NO_SUBALLOC, SPARSE. */
+    if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
         return -1;
 
     switch (domain) {
     case RADEON_DOMAIN_VRAM:
-        return RADEON_HEAP_VRAM;
+        if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+            return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+        else
+            return RADEON_HEAP_VRAM;
     case RADEON_DOMAIN_VRAM_GTT:
         return RADEON_HEAP_VRAM_GTT;
     case RADEON_DOMAIN_GTT:
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index d99081c436..8e1bc8ed98 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1138,6 +1138,9 @@ amdgpu_bo_create(struct radeon_winsys *rws,
    /* VRAM implies WC. This is not optional. */
    assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
 
+   /* NO_CPU_ACCESS is valid with VRAM only. */
+   assert(domain == RADEON_DOMAIN_VRAM || !(flags & RADEON_FLAG_NO_CPU_ACCESS));
+
    /* Sub-allocate small buffers from slabs. */
    if (!(flags & (RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_SPARSE)) &&
        size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index c516df05d8..91f09b9f5d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -925,6 +925,9 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
     /* VRAM implies WC. This is not optional. */
     if (domain & RADEON_DOMAIN_VRAM)
         flags |= RADEON_FLAG_GTT_WC;
+    /* NO_CPU_ACCESS is valid with VRAM only. */
+    if (domain != RADEON_DOMAIN_VRAM)
+        flags &= ~RADEON_FLAG_NO_CPU_ACCESS;
 
     /* Sub-allocate small buffers from slabs. */
     if (!(flags & RADEON_FLAG_NO_SUBALLOC) &&