Mesa (master): a5xx: set uint/sint bits for mrt output register

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: a00727ab25958a2fbb3c84c28db9647ab5dd1e8d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a00727ab25958a2fbb3c84c28db9647ab5dd1e8d

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Fri Jul  7 00:19:03 2017 -0400

a5xx: set uint/sint bits for mrt output register

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/freedreno/a5xx/a5xx.xml.h | 4 +++-
 src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 6 +++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
index 73e50868f7..5203799bd2 100644
--- a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
+++ b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h
@@ -8,7 +8,7 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 141764 bytes, from 2017-07-05 00:40:13)
+- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 141876 bytes, from 2017-07-07 04:12:33)
 - /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-11 01:04:14)
 - /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-07-04 02:59:47)
 - /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-07-04 02:59:47)
@@ -4096,6 +4096,8 @@ static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
 {
 	return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
 }
+#define A5XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
+#define A5XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB				0x00000400
 
 #define REG_A5XX_UNKNOWN_E5DB					0x0000e5db
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index d82315a708..c623b572be 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -58,7 +58,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 	for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
 		enum a5xx_color_fmt format = 0;
 		enum a3xx_color_swap swap = WZYX;
-		bool srgb = false;
+		bool srgb = false, sint = false, uint = false;
 		struct fd_resource *rsc = NULL;
 		struct fd_resource_slice *slice = NULL;
 		uint32_t stride = 0;
@@ -76,6 +76,8 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 			format = fd5_pipe2color(pformat);
 			swap = fd5_pipe2swap(pformat);
 			srgb = util_format_is_srgb(pformat);
+			sint = util_format_is_pure_sint(pformat);
+			uint = util_format_is_pure_uint(pformat);
 
 			debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 
@@ -110,6 +112,8 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
 
 		OUT_PKT4(ring, REG_A5XX_SP_FS_MRT_REG(i), 1);
 		OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
+				COND(sint, A5XX_SP_FS_MRT_REG_COLOR_SINT) |
+				COND(uint, A5XX_SP_FS_MRT_REG_COLOR_UINT) |
 				COND(srgb, A5XX_SP_FS_MRT_REG_COLOR_SRGB));
 
 		/* when we support UBWC, these would be the system memory