Mesa (master): radv: remove radeon_surf_level::nblk_z

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e156eaedb4a9c018c6381c1d59743ec2659aff37
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e156eaedb4a9c018c6381c1d59743ec2659aff37

Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date:   Wed May 10 22:25:15 2017 +0200

radv: remove radeon_surf_level::nblk_z

We're not using thick tiling modes, so we can just derive the value
ourselves.

Reviewed-by: Dave Airlie <airlied at redhat.com>

---

 src/amd/vulkan/radv_image.c                        | 2 +-
 src/amd/vulkan/radv_radeon_winsys.h                | 1 -
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 4 ----
 3 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 842f2919ca..ced88b980f 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -854,7 +854,7 @@ void radv_GetImageSubresourceLayout(
 	pLayout->depthPitch = surface->level[level].slice_size;
 	pLayout->size = surface->level[level].slice_size;
 	if (image->type == VK_IMAGE_TYPE_3D)
-		pLayout->size *= surface->level[level].nblk_z;
+		pLayout->size *= u_minify(image->info.depth, level);
 }
 
 
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 365ff1160f..b4fc78197d 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -169,7 +169,6 @@ struct radeon_surf_level {
 	uint64_t                    slice_size;
 	uint32_t                    nblk_x;
 	uint32_t                    nblk_y;
-	uint32_t                    nblk_z;
 	uint32_t                    mode;
 	uint64_t                    dcc_offset;
 	uint64_t                    dcc_fast_clear_size;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index ab1f9520b4..44b1c8f619 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -205,10 +205,6 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
 	surf_level->slice_size = AddrSurfInfoOut->sliceSize;
 	surf_level->nblk_x = AddrSurfInfoOut->pitch;
 	surf_level->nblk_y = AddrSurfInfoOut->height;
-	if (type == RADEON_SURF_TYPE_3D)
-		surf_level->nblk_z = AddrSurfInfoOut->depth;
-	else
-		surf_level->nblk_z = 1;
 
 	switch (AddrSurfInfoOut->tileMode) {
 	case ADDR_TM_LINEAR_ALIGNED: