Mesa (master): anv/blorp: Move the depth cache flush outside of BLORP
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Wed Jun 7 15:55:45 UTC 2017
Module: Mesa
Branch: master
Commit: ed5801864ede0a04fb5fa80bf9ffea40e5c0e022
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed5801864ede0a04fb5fa80bf9ffea40e5c0e022
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Apr 27 16:22:03 2017 -0700
anv/blorp: Move the depth cache flush outside of BLORP
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
---
src/intel/blorp/blorp_genX_exec.h | 8 --------
src/intel/vulkan/anv_blorp.c | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index a354cea117..2276d7c06b 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1500,14 +1500,6 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
}
blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp);
-
- /* Perform depth clear specific flushing */
- if (params->hiz_op == BLORP_HIZ_OP_DEPTH_CLEAR && params->depth.enabled) {
- blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
- pc.DepthStallEnable = true;
- pc.DepthCacheFlushEnable = true;
- }
- }
}
#endif
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d94a2f89fa..a869eebc24 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1323,6 +1323,22 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
clear_depth, clear_stencil,
clear_att.clearValue.
depthStencil.stencil);
+
+ /* From the SKL PRM, Depth Buffer Clear:
+ *
+ * Depth Buffer Clear Workaround
+ * Depth buffer clear pass using any of the methods (WM_STATE,
+ * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+ * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+ * “set” before starting to render. DepthStall and DepthFlush are
+ * not needed between consecutive depth clear passes nor is it
+ * required if the depth-clear pass was done with “full_surf_clear”
+ * bit set in the 3DSTATE_WM_HZ_OP.
+ */
+ if (clear_depth) {
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+ }
}
}
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