Mesa (master): freedreno/a5xx: set SP_BLEND_CONTROL properly

[Rob Clark]

Module: Mesa
Branch: master
Commit: 812fd1aaa8451938dc411b4cdb58acf2d358372c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=812fd1aaa8451938dc411b4cdb58acf2d358372c

Author: Rob Clark <robdclark at gmail.com>
Date:   Tue Jun  6 13:15:02 2017 -0400

freedreno/a5xx: set SP_BLEND_CONTROL properly

Signed-off-by: Rob Clark <robdclark at gmail.com>

---

 src/gallium/drivers/freedreno/a5xx/fd5_blend.c | 2 ++
 src/gallium/drivers/freedreno/a5xx/fd5_blend.h | 1 +
 src/gallium/drivers/freedreno/a5xx/fd5_emit.c  | 2 +-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blend.c b/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
index 42918f753a..25d9946fb1 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
@@ -142,6 +142,8 @@ fd5_blend_state_create(struct pipe_context *pctx,
 
 	so->rb_blend_cntl = A5XX_RB_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
 		COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
+	so->sp_blend_cntl = A5XX_SP_BLEND_CNTL_UNK8 |
+		COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
 
 	return so;
 }
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blend.h b/src/gallium/drivers/freedreno/a5xx/fd5_blend.h
index f758738f19..6985495485 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blend.h
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blend.h
@@ -46,6 +46,7 @@ struct fd5_blend_stateobj {
 		uint32_t blend_control_alpha;
 	} rb_mrt[A5XX_MAX_RENDER_TARGETS];
 	uint32_t rb_blend_cntl;
+	uint32_t sp_blend_cntl;
 	bool lrz_write;
 };
 
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
index 0f65802d6a..f5c0bd27c3 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c
@@ -694,7 +694,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 				A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
 
 		OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
-		OUT_RING(ring, 0x00000100);
+		OUT_RING(ring, blend->sp_blend_cntl);
 	}
 
 	if (dirty & FD_DIRTY_BLEND_COLOR) {