Mesa (master): i965/cnl: Implement depth count workaround

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: 640f5d39570daee08ad56a445fa4cd6c97ca50c8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=640f5d39570daee08ad56a445fa4cd6c97ca50c8

Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Mon Jan  4 10:48:39 2016 -0800

i965/cnl: Implement depth count workaround

Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

---

 src/mesa/drivers/dri/i965/brw_queryobj.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index a7b896243d..9ad4779322 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -111,6 +111,14 @@ brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx)
    if (brw->gen == 9 && brw->gt == 4)
       flags |= PIPE_CONTROL_CS_STALL;
 
+   if (brw->gen >= 10) {
+      /* "Driver must program PIPE_CONTROL with only Depth Stall Enable bit set
+       * prior to programming a PIPE_CONTROL with Write PS Depth Count Post sync
+       * operation."
+       */
+      brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+   }
+
    brw_emit_pipe_control_write(brw, flags,
                                query_bo, idx * sizeof(uint64_t),
                                0, 0);