Mesa (master): i965: Take a uint64_t immediate in emit_pipe_control_write
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Wed Jun 14 22:11:54 UTC 2017
Module: Mesa
Branch: master
Commit: a8ea68bc930f212dddf78a4e2073bcbd698b9140
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8ea68bc930f212dddf78a4e2073bcbd698b9140
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Jun 13 09:56:31 2017 -0700
i965: Take a uint64_t immediate in emit_pipe_control_write
It's a 64-bit value. Splitting it up just makes the function arguments
awkward.
Cc: "17.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_pipe_control.c | 22 ++++++++++------------
src/mesa/drivers/dri/i965/brw_queryobj.c | 5 ++---
src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
4 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index dc4bc8fb85..aab100e45e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1653,7 +1653,7 @@ void brw_fini_pipe_control(struct brw_context *brw);
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset,
- uint32_t imm_lower, uint32_t imm_upper);
+ uint64_t imm);
void brw_emit_mi_flush(struct brw_context *brw);
void brw_emit_post_sync_nonzero_flush(struct brw_context *brw);
void brw_emit_depth_stall_flushes(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index f4ede2deb3..0e206c683f 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -178,7 +178,7 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
void
brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset,
- uint32_t imm_lower, uint32_t imm_upper)
+ uint64_t imm)
{
if (brw->gen >= 8) {
if (brw->gen == 8)
@@ -189,8 +189,8 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(flags);
OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset);
- OUT_BATCH(imm_lower);
- OUT_BATCH(imm_upper);
+ OUT_BATCH(imm);
+ OUT_BATCH(imm >> 32);
ADVANCE_BATCH();
} else if (brw->gen >= 6) {
flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
@@ -205,16 +205,16 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(flags);
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
gen6_gtt | offset);
- OUT_BATCH(imm_lower);
- OUT_BATCH(imm_upper);
+ OUT_BATCH(imm);
+ OUT_BATCH(imm >> 32);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
- OUT_BATCH(imm_lower);
- OUT_BATCH(imm_upper);
+ OUT_BATCH(imm);
+ OUT_BATCH(imm >> 32);
ADVANCE_BATCH();
}
}
@@ -264,8 +264,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE
| PIPE_CONTROL_DEPTH_STALL,
- brw->workaround_bo, 0,
- 0, 0);
+ brw->workaround_bo, 0, 0);
}
@@ -278,8 +277,7 @@ gen7_emit_cs_stall_flush(struct brw_context *brw)
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0,
- 0, 0);
+ brw->workaround_bo, 0, 0);
}
@@ -328,7 +326,7 @@ brw_emit_post_sync_nonzero_flush(struct brw_context *brw)
PIPE_CONTROL_STALL_AT_SCOREBOARD);
brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE,
- brw->workaround_bo, 0, 0, 0);
+ brw->workaround_bo, 0, 0);
}
/* Emit a pipelined flush to either flush render and texture cache for
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 9ad4779322..bccd33b9d3 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -97,7 +97,7 @@ brw_write_timestamp(struct brw_context *brw, struct brw_bo *query_bo, int idx)
flags |= PIPE_CONTROL_CS_STALL;
brw_emit_pipe_control_write(brw, flags,
- query_bo, idx * sizeof(uint64_t), 0, 0);
+ query_bo, idx * sizeof(uint64_t), 0);
}
/**
@@ -120,8 +120,7 @@ brw_write_depth_count(struct brw_context *brw, struct brw_bo *query_bo, int idx)
}
brw_emit_pipe_control_write(brw, flags,
- query_bo, idx * sizeof(uint64_t),
- 0, 0);
+ query_bo, idx * sizeof(uint64_t), 0);
}
/**
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 4fd30ec064..8e639cfeef 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -72,7 +72,7 @@ set_query_availability(struct brw_context *brw, struct brw_query_object *query,
brw_emit_pipe_control_write(brw, flags,
query->bo, 2 * sizeof(uint64_t),
- available, 0);
+ available);
}
}
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