Mesa (master): i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 96e7b7ac54bd2220905656a0304eed2a753fceee
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96e7b7ac54bd2220905656a0304eed2a753fceee

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Jun 13 10:19:56 2017 -0700

i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS

Cc: "17.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_misc_state.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 97b6bbf5df..df52165210 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -883,13 +883,19 @@ brw_upload_state_base_address(struct brw_context *brw)
        * and flushes prior to executing our batch.  However, it doesn't seem
        * as if the kernel's flushing is always sufficient and we don't want to
        * rely on it.
+       *
+       * We make this an end-of-pipe sync instead of a normal flush because we
+       * do not know the current status of the GPU.  On Haswell at least,
+       * having a fast-clear operation in flight at the same time as a normal
+       * rendering operation can cause hangs.  Since the kernel's flushing is
+       * insufficient, we need to ensure that any rendering operations from
+       * other processes are definitely complete before we try to do our own
+       * rendering.  It's a bit of a big hammer but it appears to work.
        */
-      brw_emit_pipe_control_flush(brw,
-                                  PIPE_CONTROL_RENDER_TARGET_FLUSH |
-                                  PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-                                  dc_flush |
-                                  PIPE_CONTROL_NO_WRITE |
-                                  PIPE_CONTROL_CS_STALL);
+      brw_emit_end_of_pipe_sync(brw,
+                                PIPE_CONTROL_RENDER_TARGET_FLUSH |
+                                PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                dc_flush);
    }
 
    if (brw->gen >= 8) {