Mesa (master): intel/genxml: Add Gen10 CACHE_MODE_1 definitions

Anuj Phogat aphogat at kemper.freedesktop.org
Thu Jun 22 21:24:30 UTC 2017


Module: Mesa
Branch: master
Commit: ceed55e7bba30b60a727309616d6f7e3c2e48a5a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ceed55e7bba30b60a727309616d6f7e3c2e48a5a

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Mon Jun  5 08:31:01 2017 -0700

intel/genxml: Add Gen10 CACHE_MODE_1 definitions

Few of the fields in this register are changed as compared
to gen9.xml.

V2: Remove some fields which are not valid anymore.

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>

---

 src/intel/genxml/gen10.xml | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index d2bb130004..a19674a435 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3734,4 +3734,22 @@
     <field name="Sampler L2 Disable Mask" start="31" end="31" type="bool"/>
   </register>
 
+  <register name="CACHE_MODE_1" length="1" num="0x7004">
+    <field name="Partial Resolve Disable In VC" start="1" end="1" type="bool"/>
+    <field name="RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable" start="3" end="3" type="bool"/>
+    <field name="MCS Cache Disable" start="5" end="5" type="bool"/>
+    <field name="MSC RAW Hazard Avoidance Bit" start="9" end="9" type="bool"/>
+    <field name="NP Early Z Fails Disable" start="13" end="13" type="uint"/>
+    <field name="Blend Optimization Fix Disable" start="14" end="14" type="bool"/>
+    <field name="Color Compression Disable" start="15" end="15" type="bool"/>
+
+    <field name="Partial Resolve Disable In VC Mask" start="17" end="17" type="bool"/>
+    <field name="RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable Mask" start="19" end="19" type="bool"/>
+    <field name="MCS Cache Disable Mask" start="21" end="21" type="bool"/>
+    <field name="MSC RAW Hazard Avoidance Bit Mask" start="25" end="25" type="bool"/>
+    <field name="NP Early Z Fails Disable Mask" start="29" end="29" type="bool"/>
+    <field name="Blend Optimization Fix Disable Mask" start="30" end="30" type="bool"/>
+    <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
+  </register>
+
 </genxml>




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