Mesa (master): Revert "radeonsi: don' t emit partial flushes at the end of IBs (v2)"
Marek Olšák
mareko at kemper.freedesktop.org
Fri Jun 23 17:14:36 UTC 2017
Module: Mesa
Branch: master
Commit: c2f82fc1d3c401cf44fb94aa3ea531ca9cd0cb46
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2f82fc1d3c401cf44fb94aa3ea531ca9cd0cb46
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 23 19:02:32 2017 +0200
Revert "radeonsi: don't emit partial flushes at the end of IBs (v2)"
This reverts commit c9040dc9e75c81024f88f3f1bab821ad2bc73db3.
People have reported it causes corruption on VI, and I see GPU hangs
on GFX9.
---
src/gallium/drivers/radeonsi/si_hw_context.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c
index 76b295f9ec..345825af00 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -129,17 +129,13 @@ void si_context_gfx_flush(void *context, unsigned flags,
r600_preflush_suspend_features(&ctx->b);
+ ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
+ SI_CONTEXT_PS_PARTIAL_FLUSH;
+
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
- if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) {
- ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
- SI_CONTEXT_CS_PARTIAL_FLUSH |
- SI_CONTEXT_INV_GLOBAL_L2 |
+ if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
+ ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
SI_CONTEXT_INV_VMEM_L1;
- } else if (ctx->b.chip_class == SI) {
- /* The kernel doesn't wait for idle before doing SURFACE_SYNC. */
- ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
- SI_CONTEXT_CS_PARTIAL_FLUSH;
- }
si_emit_cache_flush(ctx);
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