Mesa (master): anv/cnl: Don't write to Cache Mode Register 1 on gen10+
Anuj Phogat
aphogat at kemper.freedesktop.org
Fri Jun 23 18:20:34 UTC 2017
Module: Mesa
Branch: master
Commit: 7896dee349bf747f5c03a9f5206a548b7482e72c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7896dee349bf747f5c03a9f5206a548b7482e72c
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Jun 13 17:01:16 2017 -0700
anv/cnl: Don't write to Cache Mode Register 1 on gen10+
For PartialResolveDisableInVC field recommendation is to
always set this to 0 and that's the default value of the bit.
So, we have nothing left to write to CACHE_MODE_1.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/intel/vulkan/genX_state.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 7a16ec06f7..3e6583289b 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -52,13 +52,11 @@ genX(init_device_state)(struct anv_device *device)
ps.PipelineSelection = _3D;
}
-#if GEN_GEN >= 9
+#if GEN_GEN == 9
uint32_t cache_mode_1;
anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
-#if GEN_GEN == 9
.FloatBlendOptimizationEnable = true,
.FloatBlendOptimizationEnableMask = true,
-#endif
.PartialResolveDisableInVC = true,
.PartialResolveDisableInVCMask = true);
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