Mesa (master): radeon/UVD: fix the decoding target pitch calculation

[Christian König]

Module: Mesa
Branch: master
Commit: 3e1e441aa05069e3eee906144cf96898e0b802e2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e1e441aa05069e3eee906144cf96898e0b802e2

Author: Christian König <christian.koenig at amd.com>
Date:   Wed Mar  8 12:51:13 2017 +0100

radeon/UVD: fix the decoding target pitch calculation

The firmware expects the value in pixel not bytes. Didn't made a difference
so far because we only used 8bpp surfaces.

Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Mark Thompson <sw at jkqxz.net>

---

 src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index f1339d1..7a08c81 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -1354,7 +1354,7 @@ static unsigned bank_wh(unsigned bankwh)
 void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
 			  struct radeon_surf *chroma)
 {
-	msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe;
+	msg->body.decode.dt_pitch = luma->level[0].nblk_x;
 	switch (luma->level[0].mode) {
 	case RADEON_SURF_MODE_LINEAR_ALIGNED:
 		msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;