Mesa (17.0): 42 new commits
Emil Velikov
evelikov at kemper.freedesktop.org
Fri Mar 17 18:07:16 UTC 2017
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07adc57fe07b3478566dbadab9b9595af3b46944
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Mar 15 18:49:29 2017 +0100
Revert "radv: Emit cache flushes before CP DMA."
This reverts commit cce43f6d8c40222099badaf52344d6a0eed993f3.
Redundant, as the flush already happens at si_cp_dma_prepare.
Acked-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit ad4dee521d7968a88393dc3685e7c593d27efba5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13afc45f8fe61467e4e97fd3164308562c7c721f
Author: Alex Smith <asmith at feralinteractive.com>
Date: Thu Mar 16 16:40:07 2017 +0000
radv/ac: Fix shared memory offset calculation
The index passed to get_shared_memory_ptr is an attribute slot index,
i.e. the index of a vec4 within LDS. Therefore this must be scaled by
sizeof(vec4) to give the LDS byte offset.
Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Alex Smith <asmith at feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
CC: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit ce4058dafd2dd283addaa99e8d5b51e53f634f9b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=06bdbe9f89fcbc1f59612da5658ff492ddb2c62a
Author: James Legg <jlegg at feralinteractive.com>
Date: Thu Mar 16 17:48:13 2017 +0000
radv: Fix using more than 4 bound descriptor sets
Avoid a buffer overflow in ac_nir_to_llvm.c's create_function when
using more than 4 descriptor sets. radv claims support for 8.
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit e88cac1df03d01a9e8a1de1a4a2ee888149e727a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=74c39635b8a9341c2607c11373fac590eca0f689
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 15 00:59:13 2017 +0100
radeonsi: disable sinking common instructions down to the end block
Initially this was a workaround for a bug introduced in LLVM 4.0
in the SimplifyCFG pass that caused image instrinsics to disappear
(because they were badly sunk). Finally, this is a win because it
decreases SGPR spilling and increases the number of waves a bit.
Although, shader-db results are good I think we might want to
remove it in the future once the issue is fixed. For now, enable
it for LLVM >= 4.0.
This also fixes a rendering issue with the speedometer in Dirt Rally.
More information can be found here https://reviews.llvm.org/D26348.
Thanks to Dave Airlie for the patch.
v2: - add a FIXME comment
- use if (HAVE_LLVM >= 0x0400) instead
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99484
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97988
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 7751ed39e40e08e5aa0633d018c9f25ad17f9bb0)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Conflicts:
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f85a54a31bd7cfa0fe615eb7302b0787dbd792eb
Author: Alex Smith <asmith at feralinteractive.com>
Date: Tue Mar 14 15:26:32 2017 +0000
radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer
Need to flush before updating the buffer to ensure that the copy is
ordered after previous accesses (assuming the app has performed the
appropriate barriers).
This fixes potential issues due to draws prior to an update reading
the new buffer content, despite having the necessary barriers between
them.
Signed-off-by: Alex Smith <asmith at feralinteractive.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit e0cc32b85bd8cf5c2202037838a208983e2d793a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=804e260859733b04aaf6d824a25d2ac047d9fc4e
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Tue Mar 14 21:46:54 2017 +0100
radv: Emit cache flushes before CP DMA.
The flushes could be due to TRANSFER barriers.
Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit cce43f6d8c40222099badaf52344d6a0eed993f3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5be65efb7b66894e055e4fce2311a71db730b12
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Mar 2 17:39:11 2017 -0800
nir/intrinsics: Make load_barycentric_input take a 2-component coor
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Cc: "17.0 13.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 60d1aac28a1f44ac166e72262e378e063155d6fd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a4b70b38408ca3e0674a7046fac1c5b0bca84b7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Mar 2 23:03:03 2017 -0800
anv/blorp: Only set a clear color for resolves if fast-cleared
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 678fd00f2f5b213d0317ba51a8163c4c5bd1f3dc)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3428b4898dfaba7c5ef2bfacd27c4e9d2ccea298
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Mar 9 16:37:23 2017 -0800
anv/blorp: Turn off AUX after doing a CCS_D resolve
For render passes with multiple subpasses on gen7, we only fast-clear at
the top but an input attachment use can cause us to do a resolve in the
middle of the render pass. Once we've done so, we are no longer have a
fast-cleared surface so we can just set aux_usage to NONE.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 273b720310863c2084c55f1371b2d27c2d96dbda)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce7f3521dee76c21e28c92ca8a8f0c09f2efdf96
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 2 04:43:21 2017 +0000
clover: Work around build failure with AltiVec.
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=587210
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68504
Acked-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit 7d1195c1e4d071fe796bf5f210c468ea1cc86225)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a11938585a7371548e96873010cb56c3ce186bb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Mar 1 11:09:30 2017 -0500
nvc0: increase alignment to 256 for texture buffers on fermi
When binding as textures, the alignment can be 16. However when binding
as an image, the address has to be aligned to 256. (Also when binding as
an RT, but that can't happen with GL or current gallium APIs.)
Reported-by: Roy Spliet <nouveau at spliet.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Acked-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 32dd8d59b6d1b6828e16e854d589d0f04536da14)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b679090a2e1548a27deccc3e38998bbb9347ea2
Author: Gregory Hainaut <gregory.hainaut at gmail.com>
Date: Mon Mar 6 15:25:32 2017 +1100
glapi: fix typo in count_scale
2*4=8
Signed-off-by: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 2ab5eccf5de4a68d0d8d2668f6c5244cc6a41846)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d74d7cc0ff517c67c3f2f55a1e625b04c4001591
Author: Jacob Lifshay <programmerjake at gmail.com>
Date: Tue Feb 28 20:30:57 2017 -0800
vulkan/wsi: Improve the DRI3 error message
This commit improves the message by telling them that they could probably
enable DRI3. More importantly, it includes a little heuristic to check
to see if we're running on AMD or NVIDIA's proprietary X11 drivers and,
if we are, doesn't emit the warning. This way, users with both a discrete
card and Intel graphics don't get the warning when they're just running
on the discrete card.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99715
Co-authored-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: Rene Lindsay <rjklindsay at hotmail.com>
Acked-by: Dave Airlie <airlied at redhat.com>
Cc: "17.0" <mesa-dev at lists.freedesktop.org>
(cherry picked from commit 3d8feb38e8fdbc05b591164cb934b48a495adfbc)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1f01d89e177ec51056b819c0aa71d49443e9fb8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 1 08:39:49 2017 -0800
anv: Properly handle destroying NULL devices and instances
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: "17.0 13.0" <mesa-dev at lists.freedesktop.org>
(cherry picked from commit e3d33a23e6cbe2b73b412a56bb4fc4aa6852d081)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d7d4f973d17d74ea9a177c09a0b70bf7370b190
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Feb 21 18:17:59 2017 -0800
anv/image: Remove extra dependency on HiZ-specific variable
surf_usage is only useful to image views that may use HiZ buffers.
Storage image views don't use HiZ buffers.
v2: Update commit message and add an assertion.
Fixes: 055ff2ec521 ("anv: Replace anv_image_has_hiz() with ISL_AUX_USAGE_HIZ")
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 258af3a856328934d30b7cdf626d5fdba76852f2)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Conflicts:
src/intel/vulkan/anv_image.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed5c3fad3778d338f0f886e87381bd9e1d3737cf
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Mar 14 06:50:59 2017 +1000
radv: setup llvm target data layout
Ported from radeonsi, pointed out by Tom.
"This prevents LLVM from using sext instructions for local memory
offsets and allows the backend to fold immediate offsets into the
instruction. This also prevents some incorrect code generation for
ptrtoint and inttoptr instructions."
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tom Stellard <tstellar at redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit b8ee70384adc3286d18febba7a92047118cc0f0f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc917075b52e5f9590cd23529ab0ead8b76cdd15
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 6 01:47:52 2017 +0100
radeonsi: mark all bound shader buffer ranges as initialized
This should prevent cases when a buffer was incorrectly mapped without
synchronization just because this wasn't done.
Cc: 13.0 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 71a2e4e9452a6890197f8b629b2d8359bdd58913)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a0f62bd652f391df2e52affbe55db34d4c17d48
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Mar 10 23:00:49 2017 -0800
anv: Stall before fast-clear operations
During initial CCS bring-up, I discovered that you have to do a full CS
stall prior to doing a CCS resolve as well as afterwards. It appears
that the same is needed for fast-clears as well. This fixes rendering
corruptions on The Talos Principle on Sky Lake GT4. The issue hasn't
been demonstrated on any other hardware however, given that this appears
to be a "too many things in the pipe" problem, having it be easier to
reproduce on a system with more EUs makes sense. The issues with
resolves is demonstrable on a GT3 or GT2 so this is probably also a
problem on all GTs.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 6b644e571e2344691e4d58ff0bba3ddc059c1a5d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2349a9e207e20c0350a217f16db61ceffa24c787
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Mar 4 10:52:43 2017 -0800
anv: Accurately advertise dynamic descriptor limits
The number of dynamic descriptors is limited by both the number of
descriptors and the total number of dynamic things. Because there isn't
a single "maximum dynamic things" limit, we need to divide by two so
that they can create the maximum of both UBOs and SSBOs.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Cc: "17.0 13.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 5e44ef4a76d9a3681fb6be605319250d4ab800ee)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f7b1160d48d5215aaa8a3826f3c37aa8c3d5c2c
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Thu Mar 9 00:38:21 2017 +0000
i965: move brw_define.h ifndef guard to the top
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 077078ce77e8653725def01ed291eb486989a9ad)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_defines.h
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5ed3f87160911bc3cc7d81954ea10a24e24824b
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Mar 7 05:08:42 2017 +0000
radv: disable mip point pre clamping.
No idea what this does, but disabling it fixes a bunch
of failing CTS tests in the lod area, so let's go with that.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit d81bd2f75462646d3803d683a28f6682a2ce3078)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=823f6d48a12c748312e46db76f8f159e42bfe622
Author: Fredrik Höglund <fredrik at kde.org>
Date: Tue Mar 7 01:53:22 2017 +0100
radv/ac: fix multiple descriptor sets with dynamic buffers
The dynamic_offset_offset in the descriptor set binding layout is
relative to the dynamic_offset_start for the set in the pipeline
layout.
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 162beb2abbe6b81d81863b3ac88ec8effcbf7c9d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=09646cce2f1850fcb3dc8790bc76466ac3087c8c
Author: Fredrik Höglund <fredrik at kde.org>
Date: Tue Mar 7 01:53:20 2017 +0100
radv: fix the dynamic buffer index in vkCmdBindDescriptorSets
This fixes the wrong dynamic buffer descriptors being updated when
firstSet > 0.
Cc: 17.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
(cherry picked from commit 0941d1a574f46c558b0037be81d9a57004f4290b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a342a47a24a331e3b4e65d21cbdf6e89f8dac7cf
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Mon Mar 6 23:23:57 2017 +0100
radv: Disable HTILE for textures with multiple layers/levels.
It has issues and the fix I'm working on is too complicated for stable,
so disable for now.
Signed-off-by: Bas Nieuwenhuizen <basni at google.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
CC: 13.0 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 0ab2dd361fd80c3840b1547cb7e05b4361eaf928)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f21cc864ba3135d7b8e6eff054b80d5f86543c61
Author: Alex Smith <asmith at feralinteractive.com>
Date: Mon Mar 6 14:54:28 2017 +0000
radv: Emit pending flushes before executing a secondary command buffer
If we have any pending flushes on the primary command buffer, these
must be performed before executing the secondary buffer.
This fixes potential corruption when the contents of a subpass which
clears any of its render targets are given in a secondary buffer: the
flushes after a fast clear would not have been performed until the
vkCmdEndRenderPass call.
Signed-off-by: Alex Smith <asmith at feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: 13.0 17.0 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 290d7e892dfa6d04767142f4f6d7ec689933a105)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9928ecaef3358d486b24809399d1a15843f6f82
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Mar 5 23:26:16 2017 +0000
radv: drop Z24 support.
This isn't exposed in -pro, the hw docs say it is deprecated,
so let's not bother with it.
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit cc59e24a6bc9bf8b51a22785beb07089770bec8d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f428040bbd45983405f67943e34f85fc3a631683
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 2 20:18:24 2017 -0500
nvc0: take extra pushbuf space into account for pushbuf_space calls
See detailed explanation of why this is needed in commit eb60a89bc3a.
This spot was missed/overlooked. Basically as a result of the fact
that BEGIN_* ends up calling PUSH_SPACE, which in turn adds an extra 8
to the requested amount, we have to be mindful of that when doing bare
nouveau_pushbuf_space calls.
Reportedly this fixes some crashes when replaying a hitman trace taken
on radeonsi.
Fixes: eb60a89bc3a ("nouveau: take extra push space into account for pushbuf_space calls")
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
Reported-by: Karol Herbst <nouveau at karolherbst.de>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
(cherry picked from commit 8e6d67685e10b001e07f92a7a6aaff4fe987b6f2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1200d64fbe7c703fbb3a0337ee8d3dcf94fe9e52
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Feb 27 10:23:33 2017 -0800
anv/pass: Avoid accessing attachment array out of bounds
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
(cherry picked from commit 178f9e5f29f3fe83eb5af99a69d7c583c30d21d1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbaf5955eee6b028e7f301dd0609a413f5aa2f3e
Author: Jonas Pfeil <pfeiljonas at gmx.de>
Date: Wed Mar 1 18:11:10 2017 +0100
ralloc: Make sure ralloc() allocations match malloc()'s alignment.
The header of ralloc needs to be aligned, because the compiler assumes
that malloc returns will be aligned to 8/16 bytes depending on the
platform, leading to degraded performance or alignment faults with ralloc.
Fixes SIGBUS on Raspberry Pi at high optimization levels.
This patch is not perfect for MSVC, as maybe in the future the alignment
for the most demanding data type might change to more than 8.
v2: Commit message reword/typo fix, and add a bigger explanation in the
code (by anholt)
Signed-off-by: Jonas Pfeil <pfeiljonas at gmx.de>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit cd2b55e536dc806f9358f71db438dd9c246cdb14)
Squashed with
ralloc: don't leave out the alignment factor
Experimentation shows that without alignment factor gcc and clang choose
a factor of 16 even on IA-32, which doesn't match what malloc() uses (8).
The problem is it makes gcc assume the pointer is 16 byte aligned, so
with -O3 it starts using aligned SSE instructions that later fault,
so always specify a suitable alignment factor.
Cc: Jonas Pfeil <pfeiljonas at gmx.de>
Fixes: cd2b55e5 "ralloc: Make sure ralloc() allocations match malloc()'s alignment."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100049
Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
Tested by: Mike Lothian <mike at fireburn.co.uk>
Tested by: Jonas Pfeil <pfeiljonas at gmx.de>
(cherry picked from commit ff494fe999510ea40e3ed5827e7818550b6de126)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e13a41d91e75df7a5527a60b4c3c8ee2976dad14
Author: Robert Foss <robert.foss at collabora.com>
Date: Wed Mar 1 19:14:39 2017 -0500
mesa: Avoid read of uninitialized variable
The is_color_attachement variable is later read when handling two
separate error cases, where only one of the cases results in the
variable being initialized.
This can be avoided by giving the variable a safe default value.
Coverity-Id: 1398631
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Robert Foss <robert.foss at collabora.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 88becf73022d780cfd0d7dbc5bb3911f8b0d2b11)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb4798d731f07207771de7cf0ac9f55eec94a809
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Feb 28 17:20:52 2017 -0800
egl: Ensure ResetNotificationStrategy matches for shared contexts.
Fixes:
dEQP-EGL.functional.robustness.negative_context.invalid_robust_shared_context_creation
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Engestrom <eric.engestrom at imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 4061bbccf2ad81612afbf8c3ded58c3b7146c5b2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9254cfa21e3f9d55e77ab19baa433ea51d618a3
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Wed Feb 22 19:59:06 2017 +0100
st/mesa: inform the driver of framebuffer changes before compute dispatches
Even though compute shaders cannot access the framebuffer, there is a
synchronization issue when a compute dispatch accesses a texture that
was previously bound and drawn to as a framebuffer.
Section 9.3 (Feedback Loops Between Textures and the Framebuffer) of
the OpenGL 4.5 spec rather implicitly clarifies that undefined behavior
results if the texture is still attached to the currently bound
framebuffer. However, the feedback loop is broken when the application
changes the framebuffer binding before a compute dispatch, and the
state tracker needs to let the driver known about this.
Fixes GL45-CTS.compute_shader.pipeline-post-fs on SI family Radeons.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 40c77bbf83a369f21c5a95f14417348aae2dbe42)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e59e2c664f3380642138bb27914237380ff778ce
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Wed Feb 22 20:04:39 2017 +0100
st/glsl_to_tgsi: avoid iterating past the head of the instruction list
exec_node::get_prev() does not guard against going past the beginning
of the list, so we need to add explicit checks here.
Found by ASAN in piglit arb_shader_storage_buffer_object-rendering.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 911391bd70fe30ad970c5e56632b2d7ccc29d955)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea7711fc0f12dd5c1ee1594884cf543b77e35cf9
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Feb 13 12:09:53 2017 +0100
i965/fs: emit MOV_INDIRECT with the source with the right register type
This was hiding bugs as it retyped the source to destination's type.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit 0dddad5b1bb3b05190074a71d274c04c0b5ea700)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1e27b0917249448a481b6681aac375505f728c3
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Thu Feb 16 10:47:01 2017 +0100
i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles
When generating the MOV INDIRECT instruction, the source type is ignored
and it is set to destination's type. However, this is going to change in a
later patch, so we need to explicitly set the proper source type.
brw_vec8_grf() creates an float type's fs_reg by default, when the
ICP handle is actually unsigned. This patch fixes these cases before
applying the aforementioned patch.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit d8122128bc6bd291ff0abcb7f2e52d9cdc631527)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59e6c0d8aee718cf58198d5a5b2adce3e01391a6
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Feb 13 13:24:18 2017 +0100
i965/fs: fix indirect load DF uniforms on BSW/BXT
The lowered BSW/BXT indirect move instructions had incorrect
source types, which luckily wasn't causing incorrect assembly to be
generated due to the bug fixed in the next patch, but would have
confused the remaining back-end IR infrastructure due to the mismatch
between the IR source types and the emitted machine code.
v2:
- Improve commit log (Curro)
- Fix read_size (Curro)
- Fix DF uniform array detection in assign_constant_locations() when
it is acceded with 32-bit MOV_INDIRECTs in BSW/BXT.
v3:
- Move changes in assign_constant_locations() to other patch.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit 56266df7ed9dbdf63acfd58944442893b4cd0c0b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d3a10c516eb5b1b4058bee4640c5fbb22617f5b
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Feb 20 11:03:46 2017 +0100
i965/fs: detect different bit size accesses to uniforms to push them in proper locations
Previously, if we had accesses with different sizes to the same uniform, we might not
push it aligned with the bigger one. This is a problem in BSW/BXT when we access
an array of DF uniform with both direct and indirect addressing because for the latter
we use 32-bit MOV INDIRECT instructions. However this problem can happen with other
generations and bitsizes.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit a497ab6838ae5a9898abfed82f7bc8295b490911)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4caa4249c28a4941e9f6a57ea97955f5d63797f
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Feb 21 08:27:30 2017 +0100
i965/fs: mark last DF uniform array element as 64 bit live one
This bug can make that we don't detect the end of a contiguous area
correctly and push larger areas than the real ones.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: "17.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit 7427425247d80c9f59a3c3ad2dfeeb2429de6f67)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6b3e73c474e57b9ba60d1319ece64c7afa48032
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Feb 22 21:39:55 2017 +0100
st/mesa: set blend state for PBO readbacks
v2: restore the state
Cc: 13.0 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
(cherry picked from commit cc2f92b09f8ab0470106185585fdc1282da523e6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b0a594369e8ce06c2f087fbd5fe1aea790dca1c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Feb 23 00:30:49 2017 +0100
st/mesa: reset sample_mask, min_sample, and render_condition for PBO ops
Cc: 13.0 17.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
(cherry picked from commit a40b76143d8b929412bed6fbed04810902844c40)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55f9cb39858a3122621ede1010331b729cfeb2a8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 21 18:28:38 2017 -0800
anv/blorp/clear_subpass: Only set surface clear color for fast clears
Not all clear colors are valid. In particular, on Broadwell and
earlier, only 0/1 colors are allowed in surface state. No CTS tests are
affected outright by this because, apparently, the CTS coverage for
different clear colors is pretty terrible. However, when multisample
compression is enabled, we do hit it with CTS tests and this commit
prevents regressions when enabling MCS on Broadwell and earlier.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: "13.0 17.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 42b10b175d5e8dfb9c4c46edbc306e7fac6bd3ec)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=579586c9267d25e06e408668e4e591399c3ff8c3
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Mar 15 18:53:24 2017 +0000
cherry-ignore: add the swizzle blorp_clear fix
Addressed an earlier commit [ccdd5b3738e] which did not land in
branch.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
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